Current Server Time: 22:52 (Central Europe)

#apertus IRC Channel Logs

2019/07/18

Timezone: UTC


03:17
Bertl_oO
off to bed now ... have a good one everyone!
03:17
Bertl_oO
changed nick to: Bertl_zZ
07:01
se6astian|away
changed nick to: se6astian
08:25
se6astian
changed nick to: se6astian|away
09:03
se6astian|away
changed nick to: se6astian
09:04
se6astian
does anyone need the remote beta setup currently and later today?
09:05
se6astian
I would take it out of the remote setup today and do some IR/UV filter tests
09:05
se6astian
let me know
09:07
aSobhy
yes I'll but it will be late ?!
09:09
se6astian
you will need it later?
09:09
se6astian
when exactly?
09:13
aSobhy
at the end of the day I assume. It depends on the simulation I'm doing now
09:14
aSobhy
22:00 CEST
09:16
se6astian
good, I should long be done by then, thanks
09:17
aSobhy
It may be later than that so take your time :)
09:17
se6astian
I will have left the axiom office by 22:00 definitely :)
09:24
aSobhy
xD
10:13
se6astian
changed nick to: se6astian|away
10:16
RexOrMatrix[m]
He's not allowed out after 6pm you see.
10:22
Nira|away
changed nick to: Nira
10:24
Bertl_zZ
changed nick to: Bertl
10:24
Bertl
morning folks!
10:25
apurvanandan[m]
Good morning Bertl
10:25
apurvanandan[m]
I was waiting for you :)
10:27
Bertl
lucky me :)
10:28
apurvanandan[m]
Haha, Yesterday in so many messages maybe my message got lost.
10:30
apurvanandan[m]
I tried what you said, so when two words are transmitted alternatively, they are received correctly but there are erroneous words received during change/transit from one word to another
10:31
apurvanandan[m]
And when I increase the fequency of change, the error words take significant part of transmitted data and soon all data is errorneous.
10:31
apurvanandan[m]
So any suggestion where might the problem be?
10:31
Bertl
which means you are not in sync
10:32
apurvanandan[m]
Sync in which part
10:32
apurvanandan[m]
?
10:32
Bertl
i.e. the receiver is leading or lagging behind on the data
10:36
apurvanandan[m]
umm, I didn't get. There isn't any problem before the decoder or ddrr x4 gearing, problem is mostly probably after word formation
10:36
apurvanandan[m]
after or in word formation right?
10:36
Bertl
I'm pretty sure you are just out of sync
10:37
Bertl
how do you word synchronize sender and receiver atm?
10:39
apurvanandan[m]
What does word synchronise exactly mean? We get a wordfrom the gearing after correct bitslip, right?
10:40
Bertl
you have a generator, which starts to generate random data (as 8bit words) at some point
10:41
Bertl
those 8bit words are then converted to 10bit codes and transmitted
10:41
Bertl
on the receiver side the 10bit codes are deserialized and then decoded to 8bit words
10:42
apurvanandan[m]
Yup
10:42
Bertl
the 8bit words are then compared with 8bit words from the same generator
10:42
Bertl
how are the two generators synchronized?
10:43
apurvanandan[m]
I am not comparing the generator, remember?
10:43
apurvanandan[m]
I am printing the decoded word received
10:43
Bertl
your constant values (or alternating values) are a generator as well
10:43
Bertl
okay, so what are you sending and what are you receiving then?
10:48
apurvanandan[m]
I have sort off unplugged the comapring module(BER calculation module) ie I am just priniting the data received. So I sent two words 165 and 211 alternatively 16 times each. On the receiver side, I saw that approx 8 times correct value is printed. When there is a change from 211 to 165 or vice versa , rubbish values are printed. Maybe this is due to direct connection of 60MHz data to 100MHz FT601 :/
10:50
apurvanandan[m]
When I was using the PRNGs, I tried pretty much +-3 to see if it syncs, but it didn't then.
10:51
Bertl
you cannot simply 'connect' two clock domains
10:52
Bertl
you need to use some kind of clock domain crossing if you have different clock domains
10:52
apurvanandan[m]
But it can't be due to direct connection of FT601 without async fifo, as when I connect counter to FT601 in similar way(60MHz connected to 100MHz without async fifo), I am able to see the counting on my PC.
10:53
apurvanandan[m]
I am avoiding the async fifo currently to avoid more complications.
10:54
Bertl
well, what kind of clock domain crossing do you use?
10:56
apurvanandan[m]
I try to reduce the frequency many times. If attach flipflops clocked at 1 MHz to 100MHz FT601 then only 1 or 2 values will be corrupted right?
10:56
apurvanandan[m]
So I can check majority values for testing
10:57
apurvanandan[m]
I though for testing it shouldn't be problem
10:57
Bertl
so you are expecting corrupted data in your tests?
10:57
Bertl
well, that's obviously what you get :)
10:58
Bertl
from 60MHz to 100MHz, I'd expect half of the data to be crap
10:58
apurvanandan[m]
But why is all data right when I reduce frequency of change?
10:59
Bertl
when the data doesn't change, it doesn't matter
10:59
Bertl
constant values will be 'constant' at the clock domain crossing
10:59
apurvanandan[m]
Means I can only test BER with current setup?
11:00
Bertl
means you cannot test anything reliably with the current setup
11:01
Bertl
because everytime the output value changes, you will have a high chance of bad data
11:01
Bertl
we talked about clock domain crossing before, you definitely need to handle that properly if you want to rely on the data
11:01
apurvanandan[m]
Its frequency is 0.5 Hertz, so it remains constant for most of the times
11:01
apurvanandan[m]
BER is updated every 2 seconds
11:03
apurvanandan[m]
I shouldn't have jumped to testing
11:03
apurvanandan[m]
I will add async fifo also now
11:04
Bertl
note that lowering the clock rate doesn't really help things
11:04
Bertl
it can actually make things worse because of the increased setup and hold times
11:05
Bertl
(unless you set proper timing constraints)
11:05
Bertl
but once again, you definitely want to do a proper clock domain crossing (doesn't need to be a fifo, but probably the easiest way)
11:07
apurvanandan[m]
Okay, this will be a lesson for me :)
11:07
apurvanandan[m]
What are others ways?
11:08
Bertl
you can do a handshake
11:08
Bertl
output the value, mark it as valid once it is stable
11:09
Bertl
sample it on the other clock domain and pass back a 'done' signal
11:09
Bertl
if you are 100% sure about the clock relation and that timing will be fine, you can even do it one way
11:10
Bertl
e.g. if your data is generated at ~25MHz and the FT domain is at 100MHz, you can be sure that you will have at least one stable cycle
11:11
Bertl
toggling a signal whenever you update the data (i.e. at 25MHz) and making sure that the data is stable before the signal is toggled will allow the receiver to detect the toggle and sample the data correctly
11:26
apurvanandan[m]
Ok thanks for correcting me!
11:26
Bertl
no problem
11:42
Nira
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11:58
se6astian|away
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se6astian
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Sebastian
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test4445
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test445
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12:41
dev__
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12:44
dev__
Good afternoon BAndiT1983, I have removed videoclip class from static allocator, imageProvider where it doesn't need to be.
12:44
dev__
https://github.com/kakashi-Of-Saringan/opencine/commits/dev
12:45
dev__
Please check last commit
12:53
dev__
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se6astian
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14:34
BAndiT1983
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Nira|away
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se6astian
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se6astian
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BAndiT1983|away
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15:19
RexOrCine|away
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15:20
Bertl
off for now ... bbl
15:20
Bertl
changed nick to: Bertl_oO
15:23
se6astian
aSobhy: remote beta should be back in the remote setup
15:24
se6astian
please write to RexOrCine in case anything with it needs on site interaction with it
15:24
se6astian
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15:27
aSobhy
OK, thanks se6astian :)
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16:42
BAndiT1983
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16:50
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17:15
RexOrCine
aSobhy: Note, I'll be away from the camera in the next hour onwards... but it appears to running fine.
17:39
se6astian|away
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se6astian
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Nira|away
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RexOrCine
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18:53
se6astian|away
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BAndiT1983|away
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BAndiT1983
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BAndiT1983|away
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21:13
BAndiT1983
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21:22
se6astian
off to bed
21:22
se6astian
good night
21:22
se6astian
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21:23
Bertl_oO
nn
22:25
Kjetil
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