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| 11:21 | Bertl | morning everyone!
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| 15:44 | dmj_nova | morning Bertl
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| 15:49 | Bertl | hey, how's going?
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| 15:54 | Bertl | btw, I uploaded the code I used to test the logic analyzer connection (http://vserver.13thfloor.at/Stuff/AXIOM/logic/)
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| 15:54 | Bertl | might be useful for playing with the PMODs
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| 16:35 | dmj_nova | hmm
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| 16:36 | dmj_nova | which one is the logic analyzer connection?
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| 16:37 | Bertl | basically PMOD_a and PMOD_b are connected to a 16 port analyzer
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| 16:37 | dmj_nova | I see
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| 16:38 | Bertl | (in a somewhat unintuitive way, i.e. 4 bit blocks, big endian)
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| 16:38 | dmj_nova | huh
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| 16:40 | Bertl | so JA4 = bit 0, JA3 = bit 1, JA2 = bit 2, JA3 = bit3
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| 16:41 | Bertl | same for the lower row for bit 4 to 7
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| 16:44 | dmj_nova | okay, I see, this is outputting onto PMOD_a and PMOD_b
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| 16:49 | dmj_nova | these can also be used as inputs to the zedboard by defining them as "in" yes?
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| 16:52 | Bertl | yes, of course
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| 16:52 | Bertl | it's the same as with the switches for example
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| 16:53 | Bertl | (they are used as inputs)
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| 17:37 | Bertl | ah, panels have returned, so the pmod debug boards will be depanelized and shipped within the next 48 hours
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| 17:40 | Bertl | dmj_nova: if everything turns out fine, and you still want to solder them yourself, you can get 3 of them for 6.85 USD
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| 17:40 | Bertl | (but I suggest you wait till I built and tested the first one)
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| 17:47 | dmj_nova | Yeah, I think I'll wait
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| 17:48 | dmj_nova | Especially since I've got another 2 weeks that I need to be working on my class stuff
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| 18:56 | dmj_nova | woot!
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| 18:56 | dmj_nova | I've got pmod inputs!
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| 19:26 | Bertl | congrats!
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| 19:47 | dmj_nova | As of this evening I'll be gone until Sunday
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| 19:48 | Bertl | okay, have fun!
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| 19:48 | dmj_nova | Such a busy summer :P
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| 20:36 | dmj_nova | left the channel |