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#apertus IRC Channel Logs

2019/06/18

Timezone: UTC


05:16
BAndiT1983|away
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05:45
Bertl_oO
off to bed now ... have a good one everyone!
05:45
Bertl_oO
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06:09
BAndiT1983
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se6astian|away
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Nira
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se6astian
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se6astian|away
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12:55
Bertl_zZ
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12:55
Bertl
morning folks!
13:30
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illwieckz_
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14:27
Y_G
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14:28
Y_G
Hi Bertl,
14:28
Y_G
about this "ZED_5V 4.7656 V [1e80] +8.8672 mV [0e3] +443.36 mA"
14:28
Y_G
you said yesterday "[0e3] is the value read from another register" ,which register is this ?
14:35
intrac
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14:44
Bertl
http://ww1.microchip.com/downloads/en/DeviceDoc/20005386B.pdf
14:45
Bertl
this is the chip we are currently using for the power measurements
14:45
comradekingu
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14:45
Bertl
there are six of those on the power board I2C bus
14:47
Bertl
on addresses 0x48-0x4d and five more on addresses 0x29-0x2d
14:48
Bertl
the registers of each pac1720 are described in section 6.0 of the datasheet (page 23)
14:49
Bertl
some of those need to be written to, but most are read ony
14:53
Y_G
Got it ,Thanks
14:54
Y_G
According to the usage you specified yesterday. I think it would be better to have commands like:
14:54
Y_G
`get pac1720_info` --> returns the result of all pac1720 sensors (this would help in getting info about all sensors at once)
14:54
Y_G
`get ZED_5v_info` ,`get HDN_info` ,`get HDS_info` .. and similar for individual sensor info.
14:55
Y_G
and `get totalPowerConsumption` --> for total power consumption.
14:58
Bertl
that's fine with me, as long as there is some way to do low level settings as well
14:59
Y_G
low level settings as in ?
14:59
Bertl
i.e. for somebody working with the pac1720 (e.g. for doing specific power measurements) there needs to be some direct register access to the I2C register map
15:00
Bertl
otherwise you can't set the resolution or sampling time, etc
15:02
Y_G
You want these control in daemon ?
15:03
Bertl
well, you don't want to have to disable the entire daemon just to do some power measurements do you?
15:03
Bertl
the main purpose of the daemon is to have a central place for coordinated access to registers
15:04
Bertl
from my point of view it would be sufficient to allow register access to those I2C devices (as the scripts already process the data)
15:05
Bertl
but if the daemon has some mechanisms to interpret this data, that is fine as well, as long as it doesn't interfere with low level access
15:06
Y_G
direct register access to has been added to it , you can set and get values to/from given the i2cbus,chipAddress,and Data address
15:07
Y_G
If that's what you mean
15:09
Bertl
great, if that work then it's fine
15:10
Bertl
in the future, it might be useful to 'claim' exclusive access to a chip to make sure that nobody else is messing with it
15:12
Y_G
Will add it to-do list .
15:12
Y_G
Thanks for the help :)
15:21
Bertl
no problem!
15:22
Bertl
btw, last time, se6astian just didn't receive your request because of technical problems
15:22
Bertl
so if you are still interested in a chat session, feel free to raise the issue again :)
15:27
se6astian
we had a brief chat already yesterday
15:27
se6astian
unless new topics have arrisen :)
15:27
se6astian
have to leave in about 30 minutes though
15:30
Y_G
Not at the moment ,if required will ping here
15:35
se6astian
great
15:42
Y_G
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se6astian
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16:53
se6astian|away
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se6astian
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18:02
aSobhy
evening Bertl
18:02
aSobhy
Can I have 5 mins just I'm finishing the last two slides :)
18:05
illwieckz_
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niemand
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niemand
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niemand
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18:22
aSobhy
I'm ready :)
19:05
Bertl
soory, had a network outage
19:05
Bertl
please go ahead
19:11
aSobhy
no problem :)
19:12
aSobhy
here is the slides I made
19:12
aSobhy
https://docs.google.com/presentation/d/1UQXrzMXU7jXEt_B0NVB3Nae7i9QpafJVaCH6rUjxSA8/edit?usp=sharing
19:14
Bertl
okay, let's hear then ...
19:15
aSobhy
Hi every one today I'll talk about JTAG
19:18
aSobhy
JTAG is a protocol that is used for verifying designs ,
19:18
aSobhy
testing printed circuit boards after manufacture and program devices in-circuit
19:18
aSobhy
slide 2
19:18
se6astian
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19:19
aSobhy
JTAG devices can be set with 2 ways
19:19
aSobhy
1- Daisy-chained
19:19
aSobhy
slide 3
19:20
aSobhy
as we can see it has a four signals that are :
19:22
aSobhy
TCK is the shared clock between all devices (Input)
19:22
aSobhy
TMS is the controll of the TAP (Input)
19:22
aSobhy
TDI is the data input to our module (Input)
19:22
aSobhy
TDO is the output of our modules (output)
19:23
se6astian
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19:23
aSobhy
as we can see that every device the TDO is the TDI input of Device2
19:24
aSobhy
so its called a Daisy-chained
19:24
Bertl
what is daisy-chaining?
19:26
aSobhy
all the devices are in chain !
19:27
aSobhy
they form a ring
19:28
aSobhy
continue ?
19:29
Bertl
yup
19:29
apurvanandan
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19:29
aSobhy
at every clock cycle of TCK : the TMS and TDI are shifted in
19:29
aSobhy
and the TDO is shifted out
19:30
aSobhy
their is an optional signal "TRST" that is for reset
19:32
aSobhy
its an optional because we can achieve resetting our device without using it as we will see
19:32
Bertl
k
19:32
aSobhy
slide4
19:33
aSobhy
Reduced pin count here we are using 2 pins
19:33
aSobhy
the connection of devices is a star connections
19:33
Bertl
this is actually a different standard we do not use
19:34
Bertl
1149.7 vs 1149.1
19:34
aSobhy
skip ?
19:34
Bertl
yeah
19:34
aSobhy
ok
19:35
aSobhy
slide 6 is swaping with slide 5 so
19:35
aSobhy
slide 6
19:35
aSobhy
here is our architecture of the JTAG
19:38
aSobhy
as an overview
19:38
aSobhy
TAP : select from the (Instruction Register)IR or (Data Register)DR
19:38
aSobhy
Instruction Register : holds which DR to operate next time
19:38
aSobhy
we will dive in each one
19:38
aSobhy
slide 5
19:39
aSobhy
the Test Access Port(TAP)
19:40
aSobhy
every device or module using JTAG must have a TAP which is a state machine controlled by the TMS and TCK
19:41
aSobhy
for illustration slide 7
19:41
aSobhy
here is the state machine we can describe it as 16 state
19:42
aSobhy
with a 6 stable state that we can stay in it more than one cycle
19:43
aSobhy
those who have a loop on them most of them looping on 0 value except for Test-logic-Reset
19:44
aSobhy
the value on arches is the value of TMS
19:44
Bertl
okay
19:45
Bertl
so what can we do with this state machine?
19:45
aSobhy
the rest of the states are changed by the TCK (every cycle )
19:46
aSobhy
we have 2 ways we can access the IR or the DR
19:46
aSobhy
forget about the last line its not in its place
19:48
Bertl
so let's say we want to write something into the IR, how would we go about that?
19:48
aSobhy
I mentioned that we can replace TRST with another method
19:49
aSobhy
so if we sent 5 1s at most we would be in the rest state
19:50
aSobhy
ok lets see IR how we can write something in it
19:52
aSobhy
in the test-logic-rest i can send TMS in that order 01100 I reached the shift-IR
19:53
aSobhy
at this state at ecery cycle of TCK the input TDI will shift in the IR and the LSB will shift out as TDO
19:54
aSobhy
the number of cycles I'll loop depends on the size of the IR
19:54
apurvanandan
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19:55
aSobhy
if it is of length 4 bits so i'll loop 4 times ie shifting 4 bits into the IR so I change its value
19:55
aSobhy
ok ?
19:56
Bertl
ok
19:57
aSobhy
lets see the DR
19:57
Bertl
how can you reach the test logic reset state?
19:57
aSobhy
by 5 consecutive '1'
19:58
Bertl
hmm, when on Capture DR for example
19:58
aSobhy
thats is the worst case when I'll be in either Capture-DR or Capture-IR
19:58
Bertl
the the first 1 brings me to Exit-DR, the next to Updat-DR
19:59
Bertl
so is it always 5 steps?
20:00
aSobhy
I think yes
20:00
Bertl
yes, it is essential that you can reach a 'known' state
20:01
Bertl
because you cannot check the state of the state machine
20:01
aSobhy
yeah its a blind reset
20:01
Bertl
so sending enough '1's through TMS will ensure that you reach the Reset
20:01
Bertl
from there on, if you remember the steps, you know the state in each TAP controller on the chain
20:02
Bertl
so IIRC, last time we had the question: how do you know how many devices are in the chain?
20:04
aSobhy
thats will be the usage of the BYPASS instruction will come soon
20:04
Bertl
okay, fair enough ...
20:05
Bertl
please continue :)
20:06
aSobhy
I forgot to mention that all the taps in the devices are all in the same state every time
20:06
aSobhy
and we can use the lower device clk rate of the lowest device
20:06
aSobhy
OK
20:07
aSobhy
lets see what is the use of IR
20:08
aSobhy
the IR value will be the selection of the desired DR
20:09
aSobhy
and based on the length of that DR we will shift bits equal to its length
20:09
aSobhy
for example the ID register
20:10
aSobhy
ID is of length 32 bits so we at the Shift-DR state we will shift 32-bits in using TDI
20:11
aSobhy
ok what are the types of IR instructions
20:11
aSobhy
slide 12
20:11
Bertl
what's the purpose of shifting in 32bit via TDI when we have the ID register selected?
20:12
aSobhy
ah sorry i forgot its the ID sorry
20:12
aSobhy
I didn't write on it
20:13
aSobhy
but if their is a register that is writable I'll shift the value of the TDI in that register
20:14
Bertl
maybe let's look at the bypass instruction/register first
20:14
aSobhy
returning back to the PYPASS instruction
20:16
aSobhy
as in slide 11
20:16
aSobhy
it provide a direct pass between the TDI and TDO
20:17
aSobhy
which has a register of 1 bit that shifts the TDI in and out that value to the TDO
20:17
aSobhy
thats make a register of the number of devices that connected in the chain
20:18
Bertl
okay, so this can be used to discover how many devices there are
20:18
aSobhy
we can check the number of devices by sending number of zeros and follod by ones
20:18
aSobhy
followed*
20:18
Bertl
does it have any other purpose?
20:19
aSobhy
when the master(host) receives the one again he will count the number of devices connected
20:20
aSobhy
I think its the idle state at the reset
20:21
Bertl
well, it can also be used to 'bypass' a device
20:21
Bertl
if you want to send data to a specific device, you have to send it through the chain
20:21
apurvanandan
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20:22
aSobhy
mmmm but all the taps will be at the BYPASS ?!
20:22
Bertl
and usually you do not want the other devices to do strange things
20:22
Bertl
there is no 'bypass' tap state, you first enter the Shift-IR state
20:23
Bertl
then you shift in the 'instructions' for all devices (in a long string)
20:23
aSobhy
ah ah sorry
20:23
Bertl
if your instructions are properly arranged, all but one device goes to bypass
20:23
aSobhy
the IR that have BYPASS value will act as a /bypass
20:23
aSobhy
sorry
20:24
Bertl
discovering then length of the instruction register is another thing you need/want to do first
20:24
Bertl
which is usually done via the IDCODEs but as they are optional, sometimes you need additional information
20:24
Bertl
anyway, that wasn't so bad
20:25
Bertl
and I hope you now have a rough idea what JTAG requires for the FPGA to FPGA protocoll
20:27
aSobhy
yeah but I have a question as I'll write the JTAG protocol
20:28
aSobhy
how to specify the length of IR
20:29
aSobhy
i found some arch are used 4 bit IR and another is 7bits
20:29
aSobhy
what is the standard ?
20:29
aSobhy
IEEE 1149.7 ?
20:34
Y_G
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20:35
Bertl
1149.7 is the reduced pin count JTAG
20:35
Bertl
1149.1 is the 'normal' JTAG
20:35
Bertl
the IR length can be any number and has nothing to do with that
20:35
se6astian|away
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20:36
Bertl
you can figure out the IR length from the BSDL
20:36
Bertl
or you can 'guess' it with some tricks via testing
20:38
Bertl
s/testing/probing/
20:39
Bertl
so, for the protocol, the length of the IR register(s) needs to be variable
20:52
aSobhy
okay I'll have alook at BSDL :)
20:56
apurvanandan
So is it all for today's meeting?
20:59
Bertl
any other progress/questions/issues?
20:59
futarisIRCcloud
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21:00
Bertl
the focus for next week should be to get a solid state (code, documentation, etc) so that we have something for the first evaluation
21:01
Bertl
(where next week means for the next 6 days :)
21:02
apurvanandan
Is blogging required?
21:02
Bertl
no
21:03
Bertl
what we will check is the code and documentation provided (so make sure we can find it :) and
21:03
Bertl
how the progress is compared to the proposed timeline
21:04
Bertl
note that good code and documentation easily makes up for being behind the schedule
21:04
Bertl
it is also a good time to check and potentially adjust your personal schedule for the rest of GSoC
21:06
apurvanandan
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21:07
Bertl
as the evaluation starts on Monday and ends on Friday, it would be a good idea to finish preparations on the weekend and be responsive regarding feedback during the week
21:09
Bertl
it might also be a good idea to give the other students and mentors an overview what was done so far (best during the regular Monday meeting)
21:09
Bertl
where the problems were and what solutions have been found, etc
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21:18
apurvanandan[m]
Ok Thanks
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23:04
se6astian
off to bed, good night
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se6astian
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