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#apertus IRC Channel Logs

2015/03/18

Timezone: UTC


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Jin^eLD
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03:06
Bertl
off to bed now ... have a good one everyone!
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Bertl
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Bertl_zZ
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08:44
Bertl
morning folks!
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cbohnens
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Bertl
off for now ... bbl
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Bertl
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cbohnens|away
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intracube
afternoon
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13:33
Francky
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13:33
Francky
hi
13:34
Bertl_oO
changed nick to: Bertl
13:34
Bertl
hey Francky!
13:38
Francky
how are you ? Do you have any news about your boards ?
13:39
Bertl
I'm fine thanks! how are you?
13:40
Bertl
Yes, I found the time to compare the iCE40 and the MachXO2 and decided to go for the MachXO2
13:40
Bertl
(better availability, more functionality, less power consumption)
13:41
Bertl
I don't have a fixed interface yet (had to clean up the power management interface first) but I should have it in the next few days
13:42
Bertl
most likely it will be a 2x 2x8 header interface and we'll drop the 'power conenctors' at the top and bottom
13:43
Francky
you speak about the beta board interface for laterla additionnal boards (like pic board) right ?
13:44
Francky
lateral*
13:44
Bertl
yep
13:44
Francky
but don't you ever order a beta board ?
13:45
Bertl
hmm?
13:45
Bertl
the v0.16 boards are on the way, probably will arrive tomorrow
13:49
Francky
ok so you change the interface ? The v0.16 boards will be "proof of concept" boards ?!
13:49
Bertl
yes, it is an integral process
13:49
Bertl
each time we can test certain elements and everytime we change something, we have to change it in all affected boards
13:50
Bertl
(in this case it will be a change for beta and power board)
13:50
Francky
right !
13:54
Francky
from my part i have checked the pinout of molex sata connectors and ordered the breatout board
13:55
Francky
i have also try to play with oserdes
13:55
Francky
but i have a question
13:56
Francky
there is some "init" things to do (both on oserdes and prng blocks). How do you do this initialisation ? In a specific process ? or you integrate this into a package which integrate the oserdes or prng ?
13:58
Francky
i don't know if i'm clear :/
14:02
Bertl
I understand what you mean
14:02
Bertl
well, we can assume that we have a control processor (ARM cores) at one end at least
14:02
Bertl
so given that we make all the control elements accessible via e.g. SPI on both sides
14:03
Bertl
we can then use a simple script or C program to initialize all the necessary components
14:05
Bertl
does that make sense to you?
14:05
Francky
not really
14:06
Bertl
okay, for the final setup (data transfer bandwidth test) we have two 'ends'
14:06
Francky
in fact i was thinking about low level initialisation like, if we take the oserdes example, we need to change reset signal state, and then change the clock_enable signal state
14:07
Francky
and for the prng, we have to change 32 time the clock state and the s_in state to charge a seed number
14:07
Bertl
each end will work as transmitter or receiver (or later probably a combination of both)
14:08
Bertl
both units are connected via a number of 'data' conenctions (and maybe a clock connection)
14:08
Francky
that's was my idea
14:08
Bertl
this is the part which incorporates the serdes, the I/O ports, etc
14:09
Bertl
now, to test those units, we need two more components
14:09
Bertl
one is the PRNG, the other is an error checker
14:09
Francky
it is quite clear for me
14:09
Bertl
to make the transfer usable, we also need an encoder and decoder
14:10
Bertl
which goes between PRNG and transmitter, receiver and error checker respectively
14:10
Bertl
all those elements have a number of 'control' signals
14:10
Bertl
(this is what you are talking about, yes?)
14:11
Francky
i think yes
14:11
Bertl
there will also be some dynamic delay elements involved, which again have a certain number of control signals
14:12
Bertl
now we need to write a simple state machine (logic) to handle the various state transitions for all thos elements
14:12
Francky
why do we need to add some delay element ?
14:13
Bertl
for example, if we have source synchronous data (i.e relative to a clock signal) we need to adjust the delay per differential pair (due to differences in the pair length)
14:13
Francky
ok
14:13
Bertl
(to sample the data at the optimal time)
14:14
Bertl
now to control those state machines and registers (like the seed value), we add a simple interface (I suggested something SPI like)
14:14
Bertl
which is then controlled from outside
14:15
Bertl
(where outside is the hardened arm cores in the Zynq)
14:15
Bertl
note that we need this interface on both ends
14:17
Andrej741
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14:17
Francky
so, if i undestand right, the sender spi module will wait for arm to get a seed value, then send the seed value to the prng module and start the number generation of the module ?
14:18
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14:18
Francky
then the prng will generate a number, send it to the serdes module
14:18
Francky
the serdes module send the data on several ldvs pairs
14:18
Francky
the iserdes receive the datas
14:18
Bertl
the split happens earlier
14:18
Francky
and send the data to the error checker module
14:19
Bertl
i.e. the prng generates "bytes", those are encoded and sent via a serializer each
14:19
Francky
and the error module 1) check if the received data is the same that the sended one, 2) inform the arm throught spi if there is an error
14:19
Francky
what do you mean by encoded ?
14:19
Francky
like a protocol ?
14:19
Bertl
it is better to simply count the errors and received bytes
14:20
Bertl
and then have the arm "query" those counters
14:20
Francky
yes i simplified
14:20
Bertl
the encoder is required to get good DC or CDR details
14:20
Francky
by "inform the arm" i mean count the erros into memeory and let the arm taking these value throught spi
14:20
Bertl
http://en.wikipedia.org/wiki/8b/10b_encoding
14:20
Bertl
check this out to get an idea
14:21
Bertl
I have VHDL code for both the 8/10 encoder as well as the TMDS encoder used for HDMI
14:23
Francky
ok this encoding doesn't change the general fonctionality of the system
14:23
Francky
it is just to have a good link
14:23
Bertl
correct
14:25
Bertl
the simplest way to achieve DC ballance is for example manchester coding
14:25
Bertl
(which doubles the number of bits)
14:26
Bertl
http://en.wikipedia.org/wiki/Line_code
14:26
Bertl
here more about the basic principles
14:30
Francky
does it the encore which generate the "oserdes cock" which is used to send the data in serial mode at the appropriate speed ?
14:30
Francky
or a high level manager ?
14:31
Francky
whaou my first sentense is not undestandable
14:31
Francky
is it the encoder which*
14:33
Francky
in fact it is frenglish
14:34
Francky
i mean does the encoder generate the clock for oserdes ?
14:48
Bertl
the clock is usually generated by a PLL
14:48
Bertl
(or MMC) which creates all the necessary clock singals in proper phase relation
14:48
Bertl
the clock can then be 'enabled' via a clock buffer
14:48
Bertl
(if required)
14:54
Francky
can you tell me if this diagram represent well the architecture ? https://dl.dropboxusercontent.com/u/782577/Diagramme_prng.jpeg
14:55
Francky
i don't wite the encoder and control signals
14:55
Francky
it is just to draw a generic block design
14:56
Francky
in fact the CLK should be a clk_enable signal
14:56
Francky
and the OSERDES sould tage a pll clk in input
14:56
Francky
should take*
14:59
Francky
something like this
14:59
Francky
https://dl.dropboxusercontent.com/u/782577/Diagramme_prng.jpg
15:00
Bertl
yes, except for the missing encoder/decoder
15:01
Bertl
also note that the input clock doesn't have an iserdes
15:01
Bertl
only a delay element (at most)
15:01
Bertl
I would also suggest to simply duplicate the PRNG
15:01
Bertl
i.e. have one on the sender and another one on the receiver side
15:01
Francky
why duplicate ? To have a 64 bit ?
15:02
Bertl
so that you do not need to transfer the data
15:02
Francky
ah ok
15:02
Bertl
because once you move the receiver to a different device, it won't work that way :)
15:02
Francky
ok
15:02
Francky
and you use the seend to generate the same list of number
15:02
Francky
seed*
15:03
Bertl
the PLL should probably also be used to clock the PRNG and similar for a divided down version on the receiver side
15:03
Bertl
@seed: correct
15:03
Francky
does the clk need a oserdes or is it another thing ?
15:04
Bertl
actually the oserdes or a ddr element (for 1:2 gearing) is a good choice, as it assures that the clock travels the same path (i.e. has similar characteristics) as the data
15:04
Bertl
s/assures/ensures/
15:05
Bertl
the iserdes you drew for the clock will most likely be a PLL or MMC itself
15:05
Bertl
because you want to sync on the clock and clean up the signal to avoid problems
15:08
Francky
and you put the clk on data input and clock input of a oserdes block ? will it work ?
15:10
Bertl
for the output clock?
15:13
Francky
for the clock of the data which transmit over the lvds line
15:14
Bertl
the data gets the encoder output on the oserdes data inputs, and the clock from the PLL
15:15
Bertl
the clock output gets a fixed data pattern (e.g. 1111100000 or 1010101010) on data input and the same clock as the data lines
15:16
Bertl
we will also investigate data transmissions without separate clock signals but that only requires a little more sophisticated logic for CDR (clock data recovery)
15:16
Bertl
and we will do that later, so for now, you can assume a separate clock transfer
15:18
jucar
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15:19
Francky
something i don't undestand :
15:19
Francky
if i put a pattern 10101010 for the clock on the lvds ligne, t wil result on a square signal right ?
15:20
Francky
if i want to transmit the pattern 10101010 on the data ligne, it will result on the same square pattern
15:20
Francky
so how does the receiver will use the clock to get the data ?
15:20
Francky
it will use both the rising and falling edge of the clock ?
15:20
Francky
this should explain the delay needed
15:21
Francky
or it will need to implement a 2xpll of the clock to get a correct clock for the data ?
15:23
Bertl
the clock pattern needs at least to be doubled on the receiver
15:24
Bertl
usually you transmit a lower clock, e.g. the word clock, and generate the high speed clock via the PLL
15:25
Bertl
of course, you can also use half the clock for the data oserdes and thus generate a high frequency clock on the clock output (which is not the best idea, because it will result in bad transmission)
15:29
Francky
ok it is very clear
15:36
Francky
something like this : https://dl.dropboxusercontent.com/u/782577/Diagramme_prng.jpg
15:56
Francky
i need to go bye !
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Francky
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15:57
Bertl
yes, that looks good, note that the clock on the receiver side should be either independant from the sender, or synchronized to the data clock
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tezburma
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17:24
lab-bot
BAndiT1983 committed rOPENCINEc1f53a8c919b: - Added basic factory, adjustments ongoing - Also adjustments for preview⦠(authored by BAndiT1983).
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intracube
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philippej|away
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philippej
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19:01
lab-bot
BAndiT1983 committed rOPENCINEff70b11b91f9: - Fixed small bugs to be able to compile again (authored by BAndiT1983).
19:24
lab-bot
BAndiT1983 created T331: Implement/extend factories. http://lab.apertus.org/T331
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se6astian|away
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19:33
se6astian
good evening
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21:53
se6astian
time for bed
21:54
se6astian
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