#apertus IRC Channel Logs

how are you ? Do you have any news about your boards ?

Yes, I found the time to compare the iCE40 and the MachXO2 and decided to go for the MachXO2

I don't have a fixed interface yet (had to clean up the power management interface first) but I should have it in the next few days

you speak about the beta board interface for laterla additionnal boards (like pic board) right ?

yep

hmm?

ok so you change the interface ? The v0.16 boards will be "proof of concept" boards ?!

each time we can test certain elements and everytime we change something, we have to change it in all affected boards

right !

i have also try to play with oserdes

there is some "init" things to do (both on oserdes and prng blocks). How do you do this initialisation ? In a specific process ? or you integrate this into a package which integrate the oserdes or prng ?

I understand what you mean

so given that we make all the control elements accessible via e.g. SPI on both sides

does that make sense to you?

okay, for the final setup (data transfer bandwidth test) we have two 'ends'

and for the prng, we have to change 32 time the clock state and the s_in state to charge a seed number

both units are connected via a number of 'data' conenctions (and maybe a clock connection)

this is the part which incorporates the serdes, the I/O ports, etc

one is the PRNG, the other is an error checker

to make the transfer usable, we also need an encoder and decoder

all those elements have a number of 'control' signals

i think yes

now we need to write a simple state machine (logic) to handle the various state transitions for all thos elements

for example, if we have source synchronous data (i.e relative to a clock signal) we need to adjust the delay per differential pair (due to differences in the pair length)

(to sample the data at the optimal time)

which is then controlled from outside

note that we need this interface on both ends

so, if i undestand right, the sender spi module will wait for arm to get a seed value, then send the seed value to the prng module and start the number generation of the module ?

then the prng will generate a number, send it to the serdes module

the iserdes receive the datas

and send the data to the error checker module

and the error module 1) check if the received data is the same that the sended one, 2) inform the arm throught spi if there is an error

like a protocol ?

and then have the arm "query" those counters

the encoder is required to get good DC or CDR details

http://en.wikipedia.org/wiki/8b/10b_encoding

I have VHDL code for both the 8/10 encoder as well as the TMDS encoder used for HDMI

it is just to have a good link

the simplest way to achieve DC ballance is for example manchester coding

http://en.wikipedia.org/wiki/Line_code

does it the encore which generate the "oserdes cock" which is used to send the data in serial mode at the appropriate speed ?

whaou my first sentense is not undestandable

in fact it is frenglish

the clock is usually generated by a PLL

the clock can then be 'enabled' via a clock buffer

can you tell me if this diagram represent well the architecture ? https://dl.dropboxusercontent.com/u/782577/Diagramme_prng.jpeg

it is just to draw a generic block design

and the OSERDES sould tage a pll clk in input

something like this

yes, except for the missing encoder/decoder

only a delay element (at most)

i.e. have one on the sender and another one on the receiver side

so that you do not need to transfer the data

because once you move the receiver to a different device, it won't work that way :)

and you use the seend to generate the same list of number

the PLL should probably also be used to clock the PRNG and similar for a divided down version on the receiver side

does the clk need a oserdes or is it another thing ?

s/assures/ensures/

because you want to sync on the clock and clean up the signal to avoid problems

for the output clock?

the data gets the encoder output on the oserdes data inputs, and the clock from the PLL

we will also investigate data transmissions without separate clock signals but that only requires a little more sophisticated logic for CDR (clock data recovery)

if i put a pattern 10101010 for the clock on the lvds ligne, t wil result on a square signal right ?

so how does the receiver will use the clock to get the data ?

this should explain the delay needed

the clock pattern needs at least to be doubled on the receiver

of course, you can also use half the clock for the data oserdes and thus generate a high frequency clock on the clock output (which is not the best idea, because it will result in bad transmission)

something like this : https://dl.dropboxusercontent.com/u/782577/Diagramme_prng.jpg

BAndiT1983 committed rOPENCINEff70b11b91f9: - Fixed small bugs to be able to compile again (authored by BAndiT1983).