#apertus IRC Channel Logs

off to bed now ... have a good one everyone!

good day

morning folks!

if there are any please pm me I need your help

save!

who is here?

lets do the usual order :)

sure!

last week after the contrast shader on the visualizer display was added, i created a toggle button

Hi!

then we decided to move towards the hardware tasks, so i tested my USB code using the virtual serial ports which worked as expected

did BAndiT1983 get the USB working on the new remote?

> did BAndiT1983 get the USB working on the new remote?

that's it from me!

(JFYI)

i'll continue with my report then..

yes bluez please start in the meantime

okay! so last week i did more reading on PCAP/ICAP interfaces on the Zynq, and also revised on the frame/CLB structures etc.

yes here is the simulation -> https://lab.apertus.org/F170410

but it seems the PCAP can be used only through the 'devcfg' interface by Xilinx

so i have been trying to make it work.. not quite working yet

eppisai: ready for your turn?

last week, I chnaged the underlying approch of keyboard to suit better for capital, small, other cases and was using using string instead of array of char

isn't a string an array of characters?

it is also array of char with null character

sounds good, what are the next steps or plans?

but my network is unstable

also made the proper qwerty keyboard

nice

one thing, that i had noticed an hour ago

their is no spacebar in keyboard rightnow

good point

good question, spacebar could be useful I think

but a detail we can also add/discuss later I assume

looks good

ahh.. no thats it..

Shohei: please go ahead with your report!

I finished reading the link about the enclosure, roughly checked the relate linkes, and also

I'm coisidering to read links about PCBs listed here next since I want to get one sample in my hand.

https://wiki.apertus.org/index.php/AXIOM_Beta/PCBs

I am studying the structure of cameras of other existing models, too.

if you plan to assemble the PCBs yourself (i.e. 'build' the boards) please contact me for a preliminary check whether you have the right tools/skills there

Thank you verymuch Bertl. I will contact you then :)

ups,

let me know if you need any support in the process

Thank you again:)

Besides brainstorming ideas on how to improve the compression ratio with anuejn I worked on getting the rust implementation further along

so the rust implementation can now do the basic steps, recursive 2d wavelet transformation, quantization, runlength encoding and huffman encoding

the rust implementation can also now open 12 bit DNG files so it can read the demo real world files anuejn choose to test the compression

the next steps will be implementing the gateware optimized packing / unpacking of the compressed data in the rust implementation and then hopefully switching our experiments over to rust

right

some time in the last week we had the discussion if it wouldnt be beneficial to maintain the cineform raw standard compatibility so any software that supports it can read our files, I did some research then and discovered that the broad support for cineform raw in editing software has gone to 0 since gopro purchased it and killed it

there is no software support anymore, not even gopro itself seems to support it anymore

anuejn: please go ahead

1. Limiting the huffman codebook size and defining an 'escape symbol' after which a non-compressed symbol can follow. This is essentialy equivalent to generating a non-optimal huffman table.

2. Combining multiple frequent symbols into additional symbols

combining more than two characters brought virtually no benefit as any savings in symbol count were outwight by losses in the huffman stage

has the JPEG XL documentation brought any new ideas?

se6ast1an: not really

But I didnt try too hard

how large is the window currently required for encoding?

Bertl: for the basic algorithm about 6 rows

but then we need some buffers in addition in some places

we have been paying close attention to the required buffer size to have it work well / efficiently on a fpga

the other thing I looked into is building the micro r2.1

a great!

I guess in a few days I would be ready to start on routing the PCB

so that is something we have to discuss

Bertl: your feedback regarding R2.1 was mostly routing related right? not schematic?

I really can't remember ...

sure!

Bertl: then maybe it is best if I send you the schematic when I am done and you review it then?

fine :)

thats it from my side

quick updates from me:

so there are now different adapters that place the filter at different distances to the sensor

I will print those soon and when I have a beta in hands again can start capturing new samples again for intrac and others

should arrive on Thursday

beside various small AXIOM Remote software additions here and there

all parts have now been researched and I started ordering already today

will order the remaining distributors today or tomorrow at the latest I hope

Bertl: the finisher!

well, I finally got to testing the connector replacement for the PM-MB interface

first they do not handle heat well, so hot-air rework is 'complicated'

so we decided to replace them but only after a verification

but doesn't seem to have those drawbacks

mechanically everything looks great, electrical testing happend in the last hour and seems to work fine, although I seem to have some weird power leak on the MB, but that is likely unrelated to the connectors

I also installed the remote remote, although we are still missing the serial interface there

that's it from my side for this week

what do you mean by "power leak"?

s/unexpected/unexplained/

it definitely originates from the main board

thanks for the report

nothing there yet

anyone else who wants to share/report something

ok then, thanks everyone for the meeting, great as always!

thanks for moderating!

osqar: that should be 'BUY!' :)

heading off

but maybe the online opening hours are not correct...

See you guys

see you

Bertl: great

anuejn: now would work form me

sorry, very busy currently

off now

Bertl: with the current beta mainboard, are the clock capable pins among the lvds lanes of the plugin modules?

anytime should work for me