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| 09:31 | Bertl | morning everyone!
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| 09:33 | se6astian | Hi!
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| 11:12 | se6astian | ok dentist appointment :O
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| 11:12 | se6astian | bbl
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| 13:40 | se6astian | back
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| 13:42 | Bertl | wb
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| 13:42 | Bertl | I just uploaded the first real vivado example, featuring a bram memory mapped into the PS as axi-lite slave
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| 13:43 | Bertl | i.e. you can read/write the dual port bram (in PL) from the PS and from the PL
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| 13:44 | Bertl | http://vserver.13thfloor.at/Stuff/AXIOM/reg_bram/
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| 13:44 | se6astian | nice, I dont understand a single word but it sounds great :)
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| 13:45 | Bertl | basically its like 36kb of memory located inside the PL, which can also be accessed as 'memory' inside the PS
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| 13:45 | Bertl | but it isn't DRAM meory, it is block ram
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| 13:57 | se6astian | ok so this is like the "vorstufe" to the actual framebuffer in memory?
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| 13:58 | se6astian | but for low datarate exchange only for now (sensor parameters maybe) ?
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| 14:24 | Bertl | yep, the main purpose is to exchange a few settings between PL and PS in a controlled way
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| 14:24 | se6astian | perfect!
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