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03:45 | Bertl | off to bed now ... have a good one everyone!
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09:26 | se6astian | I am disconnecting the remote beta to test it in the compact enclosure prototype
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13:44 | Bertl_zZ | changed nick to: Bertl
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13:44 | Bertl | morning folks!
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13:51 | abeljj[m] | morning Bertl
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14:04 | Bertl | hey abeljj[m]! how's it going?
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14:48 | Y_G | Hi Bertl , I was trying to move `pac1720_info.sh` to daemon ,I can replicate the output there.
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14:48 | Y_G | However could you help me with how do you want the functionality in the daemon.
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14:48 | Y_G | As in do we want to replicate what `pac1720_info.sh` with a command like `get pac1720Info` or do we want to break it down into various parts for ex `get ZED_5V` , `get HDN` etc.
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14:49 | Bertl | I think it makes a lot sense to have it broken down to the parts
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14:49 | Bertl | but of course you can abstact away all the calculations
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14:50 | Bertl | in the future it also makes sense to have Beta specific configuration or corrections into the daemon
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14:51 | Bertl | for example, the temperate reported from the Zynq can differ about 5-10deg from the actual temeprature
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14:51 | Bertl | so once we do calibrations on those values, there will be some correction values
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14:52 | Y_G | Why does this difference in temp occur ?
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14:53 | Bertl | probably because the sensor (temp diode) inside the zynq is not properly calibrated
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14:53 | Bertl | (and of low quality regarding temperature measurement :)
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14:54 | Y_G | Ohk, So do we know these correction values currently ?
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14:55 | Bertl | they are specific for each MicroZed, we could measure them by putting the MicroZed into a heat chamber or putting an external sensor on the Zynq
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14:56 | Bertl | but this is not done currently, nevertheless, we will definitely do that in the future
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14:56 | Y_G | yes , that would be good
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14:57 | Y_G | Also about that breaking down of functionality would something like `get ZED_5v` with output as `value : 5.1562 V [2100] +14.2578 mV [16d] +712.89 mA` ,or should I break it down further
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14:59 | Bertl | well, the real question here should be: what will those values be used for
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15:00 | Bertl | typically you want to look at the voltages to see if they are correct but often you are just interested in the current power consumption (total or per power rail)
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15:01 | Bertl | the let's break down the values from the script
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15:01 | Bertl | ZED_5V 4.7656 V [1e80] +8.8672 mV [0e3] +443.36 mA
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15:01 | Bertl | [1e80] is the value read from the pac1720 register
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15:02 | Bertl | 4.7656 V is the interpretation of that value in human readable form
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15:02 | Bertl | both refer to the measured voltage
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15:02 | Bertl | similar, [0e3] is the value read from another register
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15:03 | Bertl | +8.8672 mV is the conversion to human readable form
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15:03 | Bertl | and +443.36 mA is the interpretation of that value based on the information that the board has 0.02Ohm resistors equipped for current measurements
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15:06 | Y_G | and What are these 'ZED_5V' , 'HDN' ,'HDS' .. things
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15:10 | Bertl | if you look at the Power Board schematic, there are a number of pac1720 all over it measuring various power rails
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15:10 | Bertl | the first column is an abbreviation for those rails
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15:11 | Bertl | N, E, S, and W usually refer to the location (North, East, West and South)
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15:11 | Bertl | so for example, RFW_V means Routing Fabric West supply Voltage
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15:11 | Bertl | PCIE_S_V means PCIE South Voltage
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15:12 | Bertl | the power rails for the interface and sensor board have two 'directions'
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15:12 | Bertl | so N_VW means North West Voltage rail
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15:13 | Y_G | Ok, is there some manual where I can find all these , would help alot to give suitable names to variables
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15:14 | Bertl | not sure we have anything there except for the scripts and the schematics
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15:24 | Y_G | Couldn't get anything from the schematics
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15:27 | Bertl | no problem, just ask me then :)
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15:29 | Y_G | IOW_V, VCCO_13 , HDN ,S_VS ,these should be suffice for figuring out the remaining
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15:29 | Bertl | IOW_V = I/O Voltage West
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15:30 | Bertl | VCCIO_13 is terminology from the Zynq and refers to the Bank 13 I/O voltage
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15:33 | Bertl | HDN is now called CSO_N which means Center Solder On North
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15:34 | Bertl | (or CSO_NE_V)
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15:34 | Bertl | and S_VS is one of the six power rails for Interface/SFE in this case South-South
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15:35 | Bertl | (not that S_VS exists :)
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15:35 | Bertl | the only ones with identical directions are W_VW and E_VE which are the rails for the interface board
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15:35 | Bertl | ah, ignore that comment about S_VS
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15:36 | Bertl | S_VE, S_VS and S_VW are the south side SFE supplies
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15:36 | Bertl | S_VE = South East Voltage rail, S_VS = South Voltage rail, S_VW = South West Voltage rail
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15:37 | Y_G | Thanks Bertl ,this helps alot :)
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15:37 | Bertl | np
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17:02 | Bertl | evening everyone!
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17:02 | apurvanandan[m] | Good evening!
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17:03 | Fares | good evening
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17:03 | se6astian | meeting time
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17:03 | se6astian | welcome everyone
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17:04 | aSobhy | good evening!
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17:04 | se6astian | please again message me in the good old fashion if you want to report
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17:05 | se6astian | Nira please go ahead first
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17:05 | Nira | Great!
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17:07 | Nira | this week I have been testing code on the PIC16, I thought I could make it work faster, but it has been trickier than expected
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17:08 | Nira | I will continue by doing this, and this is my last exams week, so soon I will have my full time for this!
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17:09 | Nira | I have also had a problem with the remote, so the micro USB connector has broken (it has detached from the PCB). I have already told Bertl about it in order to see how to solve it
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17:10 | Bertl | yeah, we should discuss this after the meeting in the remote channel
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17:11 | Nira | perfect, so that's all from me
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17:11 | se6astian | thanks, fares your up
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17:11 | Fares | great! hi everyone
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17:13 | Fares | I have been working on refactoring the code to allow for different configurations for different use cases. I also did two main configurations for micro and beta and those that I will be concentrating on them
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17:15 | Fares | I also coded an initial module to fix 0xFF bytes but it is not 100% finished yet, then I spent a lot of time trying to tune the design to achieve better utilization and clk rate, the code is a little messy now as I tried several different things
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17:17 | Fares | and mainly I will test one more idea then move on to complete the 0xFF fixer and do proper testing to the new code.
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17:18 | Bertl | sounds good, any preliminary conclusions regarding clock and resource usage?
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17:21 | Fares | I'm targeting 200MHZ with two pixels/clk for beta and 200MHZ with one pixel/clk for the micro, the timing is met in almost all component, some of them I needed to register the input before the logic - the components after fifo - but they work, only one module that I'm currently working on which have the big shift operation, but I believe 200MHZ is doable, the utilization should be less than 1k lut and 1k ff
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17:22 | Bertl | sounds great!
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17:22 | Fares | great! that would be all.
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17:23 | se6astian | many thanks
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17:23 | se6astian | aSobhy: your turn!
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17:24 | aSobhy | hi everyone :)
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17:24 | aSobhy | for the past week I finshed the ZYNQ side and wrote the link training at the MachXO2 side what remains is the deserializer thats I am on it
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17:24 | aSobhy | read more about jtag ,prepare for the jtag presentation i have.
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17:26 | aSobhy | thats all
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17:27 | Bertl | looking forward to it!
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17:27 | se6astian | thanks aSobhy
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17:27 | se6astian | dev__: your up next
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17:28 | dev__ | Yes, se6astian
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17:28 | dev__ | Hello Everyone !
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17:28 | dev__ | Last Week, Some refactoring for MLVLoader was done as functions like MLvLoader::load got rather big and i have commited the code also.
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17:29 | dev__ | I was also able to implement static allocator for OC playback in separate repo for just testing. Last week, I was also off because of traveling so one or two blank days was also there.
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17:30 | dev__ | Right now, i am trying to use implemented allocators for playback and I hope, It should be completed in the first half of this week.
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17:31 | dev__ | Then we can also go for adding sliders to playback
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17:31 | dev__ | Thanks !
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17:31 | se6astian | great, thanks
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17:31 | se6astian | Y_G: please go ahead
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17:32 | Y_G | Hi All ,
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17:32 | Y_G | This week I completed the I2CAdapter ,and tested it with a test module(replicates `pac1720_info.sh`) in beta.
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17:32 | Y_G | The output was as required.There are some coding standard issues that BAndiT1983|away told me and I am working on them.
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17:32 | Y_G | Also I went through the scripts to check which adapter each scripts would use when and if moved to daemon.
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17:33 | Y_G | For the initial part of this week I plan to move `gamma_conf.sh` to daemon and fix the current problem with the test Module .Further tasks for this week will be discussed with BAndiT1983|away. That's all from my side.
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17:34 | se6astian | thanks Y_G
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17:34 | se6astian | apurvanandan[m]: your turn
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17:35 | apurvanandan[m] | Hi everyone :)
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17:35 | apurvanandan[m] | This week I completed the ft601 controller for the machxo2 on the plugin module!
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17:37 | se6astian | wonderful, please share some details :)
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17:37 | apurvanandan[m] | On machXO2 I generate 32 bit count at 100 MHz that I transfer to the connected pc. The transfer is happening at full speed/capability of the ft601 chip ie at 3.2 Gbits with any data packet missing or corrupting :)
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17:39 | apurvanandan[m] | I have pushed the source of rtl for machXO2 and D3XX C++ code here --> https://github.com/apurvanandan1997/usb-plug-mod/tree/master/MachXO2
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17:39 | apurvanandan[m] | I meant without any data packet missing ie error free.
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17:40 | se6astian | sounds great!
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17:42 | apurvanandan[m] | Now I have started working on sending data from another fpga ( my Virtex-5 board) to this usb plugin module using LVDS connection ( made using dupont cable :). I will work with aSobhy and acheive some simple link training this week :)
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17:42 | apurvanandan[m] | The makefile on this repo is not working currently , I will correct that soon.
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17:42 | Bertl | okay :)
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17:42 | apurvanandan[m] | That was from my side this week :)
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17:44 | apurvanandan[m] | As next week we have our first evaluation , I would like you to discuss a little bit about it :)
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17:45 | apurvanandan[m] | On how things work and some advice you want us to follow etc.
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17:45 | apurvanandan[m] | I am done thanks for your time :)
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17:45 | se6astian | great, thanks
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17:46 | se6astian | quick updates from my side now, then Bertl might want to do the closing words again
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17:46 | se6astian | The AXIOM Beta compact enclosure prototype parts arrived mid last week and we started putting them together on friday
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17:47 | se6astian | today we put the electronics inside the enclosure as well and wanted to check if they fit and if the camera still works
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17:47 | se6astian | good news: it does :)
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17:47 | se6astian | https://cloud.gerade.org/index.php/apps/gallery/s/XK5Hj3Tg9BKWPsn#cp-asselby02.jpg
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17:47 | se6astian | https://cloud.gerade.org/index.php/apps/gallery/s/XK5Hj3Tg9BKWPsn#cp-asselby01.jpg
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17:47 | se6astian | here are some more pictures of the parts and how they arrived: https://cloud.gerade.org/index.php/apps/gallery/s/XK5Hj3Tg9BKWPsn#
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17:50 | se6astian | thats it from me for this week
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17:50 | se6astian | Bertl: ?
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17:50 | Bertl | thanks!
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17:51 | Bertl | Besides reworking and testing Betas and mentoring, I actually found some time for development
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17:52 | Bertl | I did write some test code for the new oscillator on the Axiom Remote
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17:52 | Bertl | and a demo for the USB interface on the PIC32MZ
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17:52 | Bertl | code can be found here: http://vserver.13thfloor.at/Stuff/AXIOM/REMOTE/
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17:53 | Bertl | but I'll add it to the github repository soon
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17:53 | Bertl | the current version implements a serial interface (CDC/ACM) but I think HID might be quite appealing for the remote as well
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17:54 | Bertl | I also did some material research and testing
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17:54 | Bertl | that's it from my side.
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17:55 | se6astian | great
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17:55 | se6astian | do you want to talk about the laser cutter as well?
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17:55 | Bertl | nope
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17:55 | se6astian | ok, thanks
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17:56 | se6astian | anyone else want to share/discuss anything?
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17:56 | apurvanandan[m] | Would you like to share some information about first evaluation?
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17:58 | se6astian | what "first evaluation" exactly?
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17:58 | Bertl | the GSoC evaluation coming up
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17:58 | se6astian | ah, right
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17:59 | se6astian | its something each mentor does for his students individually
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18:00 | comradekingu | se6astian: Though harder to machine, a honeycomb pattern has greater airflow
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18:00 | se6astian | if there is feedback prior to the evaluations it should be done in private between mentor/student
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18:01 | apurvanandan[m] | Ok I got it thanks :)
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18:01 | se6astian | thanks comradekingu
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18:01 | se6astian | ok I guess that concludes our meeting for today
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18:01 | comradekingu | looks good :)
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18:02 | Bertl | Nira, se6astian, BAndiT1983: let's have a short remote related chat on the remote channel
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18:03 | Kjetil | is it remotely interesting?
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18:04 | se6astian | very :)
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18:04 | Bertl | yes :)
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18:04 | se6astian | I actually have to leave very soon now
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18:04 | se6astian | a bit later in the evening?
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18:04 | Bertl | fine with me too, Nira?
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18:04 | Nira | no problem, which hour aprox?
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18:05 | Dev_ | left the channel | |
18:06 | se6astian | 20:30, 21:00 ?
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18:06 | Nira | perfect!
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18:07 | comradekingu | https://www.silverstonetek.com/techtalk_cont.php?area=en&tid=wh_chessis specifically but also https://www.pugetsystems.com/labs/articles/Effects-of-Grill-Patterns-on-Fan-Performance-Noise-107/
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18:07 | comradekingu | https://www.researchgate.net/publication/226528692_Method_for_modifying_axial_fan's_guard_grill_and_its_impact_on_operating_characteristics https://www.mouser.com/pdfDocs/passive_noise_reduction_options_for_axial_and_centrifugal_fans.pdf is the math
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18:10 | comradekingu | A design that runs water off the top plane and maintains good airflow considering the thickness of the top plate would be ideal
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18:10 | comradekingu | airflow and noise
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20:30 | Bertl | off for now ... bbl
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22:22 | se6astian | off to bed, good night
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