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#apertus IRC Channel Logs

2019/03/17

Timezone: UTC


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kwezy
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illwieckz_
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Dev_
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Bertl_oO
off to bed now ... have a good one everyone!
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Bertl_oO
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BAndiT1983|away
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BAndiT1983
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08:54
Alan_
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08:56
Alan_
Hi,I am Alan P john 3rd year information technology undergraduate intrested in gsoc29
08:57
Alan_
Gsoc19
08:58
Alan_
I am interested in T734 , I was looking into hist.c but didn't find any documentation of code.
08:59
Alan_
And readme is also very short .
09:00
Alan_
What are those hexa values and why to memory map twise ?
09:02
Alan_
"twice"
09:03
se6astian|away
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09:04
Alan_
, those variable used inside also seems hard to understand , Am I missing something ?
09:05
Alan_
If yes please direct me to source .
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Alan_
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Alan_
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09:16
Alan_
Too much of bit manipulation is taking place , o.0
09:17
Alan_
I will be checking irc logs ,
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Alan_
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09:26
vup2
Alan_: unfortunately i don't think there is a lot of documentation beyond the code itself
09:26
vup2
alot of the code also only deals with talking to the fpga and getting a image
09:27
vup2
the part calculating the histogram is at very end of hist.c starting at line 292
09:29
vup2
there are two regions that need to be memory mapped, first the region for the various parameters that control the image acquisition (the *base one)
09:29
vup2
and one memory mapped region for the buffer where the image itself will be located
09:35
Alan_
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09:38
Alan_
@vup okay understood that .
09:39
Alan_
What all things should i read about fpga to understand that part of code ,I read we use zynq 7000
09:39
vup2
for the exact explanation of the various things that deal with the image acquisition i think its best to talk to Bertl_zZ when he wakes up
09:40
vup2
Alan_: do you plan on implementing the histogram / vectorscope / waveform on the fpga?
09:40
vup2
otherwise the details of the fpga itself are probably not that interesting
09:41
Alan_
Yes , I am planing to add those features in beta firmware .
09:41
Alan_
Probably to understand the code of hist.c it will be require
09:42
Alan_
What specific things should i read about fpga to understand the code.
09:43
Alan_
As i was trying to read zynq , it is a huge topic itself
09:43
vup2
well the hdl sources for the fpga can be found here https://github.com/apertus-open-source-cinema/axiom-beta-firmware/tree/master/peripherals/soc_main
09:44
vup2
but it is probably better to wait for Bertl_zZ and let him explain the specific parts that are relevant for this task
09:44
Alan_
I would be implementing it in beta firmware using C , I also don't have much experience with HDL
09:45
vup2
the most important thing about the zynq itself is probably that it is a combination of a fpga and a arm core, which share access to the system memory
09:45
Alan_
Yes I understood that .
09:46
Alan_
One last thing first mmap is for parameter which control acquisition where to read about these ?
09:47
vup2
i don't think there these are documented in a concise way yet, you will probably need to ask Bertl_zZ for that
09:48
Alan_
Okay vup2 thank you very much for help and I will be waiting for bertl to come .
09:49
Alan_
Will be reading logs
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se6astian
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09:54
apurvanandan[m]
Hi, I have completed the Serial to parallel converter T871, pleas see into it and suggest correction if any, so that I can start documenting the code. How can I submit it?
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Dev_
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Dev_
Hey apurvanandan[m] :) , we have to submit the challenge along with proposal , although contact respective mentor to get your code checked !
12:44
Dev_
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12:44
Bertl_zZ
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12:45
Bertl
morning folks!
12:50
siddhantsahu
Morning :Bertl
12:53
siddhantsahu
Regarding the C++ challenge, Debayering will work better if we use debayering algorithms on 12 bits per pixel RAW file compared to 8 bits per pixel? Or will it be same?
12:53
Bertl
Alan_: ignoring the sensor setup and trigger, there is a memory region on the AXIOM Beta where the sensor data is transferred into buffers
12:56
Bertl
Alan_: the DDR memory is shared between FPGA and CPU (ARM cores) so the focus should be on processing this buffer data in an efficient way to reduce overall bandwidth consumption
12:57
Bertl
siddhantsahu: debayering is always 'guesswork' so with a smart algorithm you might get better results on 8bit than with a dumb algorithm on 12bit given that your output image is 8bit anyway
12:59
Bertl
apurvanandan[m]: best to double check your code (formatting, indentation, spaces, comments) and upload it somewhere (github, etc) then simply send me the link via IRC or e-mail to provide some feedback
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RexOrCine|away
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15:55
RexOrCine
Cheers Herbs.
15:56
RexOrCine
The Herb.
15:56
RexOrCine
Herbal Brownie.
16:06
BAndiT1983|away
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16:09
intrac
se6astian|away: Desaturation with PLR is a byproduct of the flattened response curve - same as when shooting log. But in both cases, when the image is graded to restore contrast, the saturation will come back.
16:10
intrac
my desaturation test is separate from that
16:13
siddhantsahu
BAndiT1983: Good Morning!
16:14
siddhantsahu
Will this https://3dlutcreator.com/index.html feature of creating LUTs great of OpenCine users?
16:16
siddhantsahu
Users can create their own LUTs (2D and 3D) and apply it to AXIOM beta footage
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se6astian|away
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16:49
BAndiT1983
hi siddhantsahu
16:50
BAndiT1983
LUt was one of planned features, but there was no implementation done yet
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BAndiT1983
off for now
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BAndiT1983
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illwieckz_
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17:42
Alan_
Hello , bertl which DDR(1,2or3) are we using in Arm? , I tried to search it on wiki but didn't find .
17:42
Alan_
And what is center sample area ?
17:45
Alan_
Why exactly we using decimetor factor , sdec and adec ?
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zaid
hello who is apinky
17:54
zaid
fuck off gsoc
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18:01
Alan_
Will be seeing logs .
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18:11
Bertl
Alan_: the AXIOM Beta uses a MicroZed with a Zynq 7020 (which I also linked in the task description)
18:12
Bertl
the microzed uses Micron MT41K256M16HA-125:EDDR3 creating a 256M x 32-bit interface at up to 1066 MT/s
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BAndiT1983|away
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se6astian
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RexOrCine
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BAndiT1983
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