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#apertus IRC Channel Logs

2020/07/16

Timezone: UTC


01:28
Spirit532
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04:11
Bertl_oO
off to bed now ... have a good one everyone!
04:12
Bertl_oO
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06:39
BAndiT1983|away
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08:11
MichaelSchwarzma
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09:01
se6ast1an
good morning
09:03
BAndiT1983
hi
11:50
mumptai
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13:22
Bertl_zZ
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13:22
Bertl
morning folks!
13:26
se6ast1an
good day!
15:55
mumptai
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mumptai
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schmoggie
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16:40
Bertl
off for now ... bbl
16:40
Bertl
changed nick to: Bertl_oO
16:45
MichaelSchwarzma
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16:48
aombk
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18:04
mithro
https://github.com/antmicro/sdi-mipi-bridge
18:05
mithro
Oh, oh! If you are rewriting the apertus gateware in nmigen then we should certainly chat!
18:11
Bertl_oO
definitely!
18:12
Bertl_oO
felix_: look, somebody implemented SDI :)
18:47
felix_
don't see any fpga design code in there though
18:51
Bertl_oO
maybe mithro knows more ...
19:07
mithro
Bertl_oO: Sadly, no still uses closed source SDI cores
19:07
Bertl_oO
that's a pity
19:12
mithro
Bertl_oO: Still working on solving that problem
19:20
felix_
i've been quite busy with my new job at AMD working on coreboot and didn't get around to continue working on photonsdi yet :(
19:27
mithro
Bertl_oO: We are getting a lot of zynq support into the open tools
19:28
mithro
@Bertl_oO: And things like partial reconfigurable regions which let you use part of the design on Vivado and part in the open tools
19:29
felix_
that sounds awesome
19:30
Bertl_oO
mithro: so do the open tools now support the zynq 7020 completely?
19:30
Bertl_oO
(last time I checked not even the fuzzers worked as expected)
19:30
mithro
Bertl_oO: Depends what you mean my "completely"?
19:31
Bertl_oO
well, AXI, SERDES, delays, etc
19:31
mithro
Bertl_oO: https://github.com/SymbiFlow/symbiflow-arch-defs/pull/1506
19:31
mithro
[Merged] Zynq 7020 support #1506
19:32
Bertl_oO
yay! not even a month ago \o/
19:32
mithro
Bertl_oO: DSP / GTPs still need to be decoded -- but the PR flow enables you to keep parts in Vivado and incrementally move more and more into the open source tools
19:33
mumptai
wonders if that finally makes the zynq self-synthesizing
19:33
Bertl_oO
mithro: parts in vivado? how does that work?
19:34
mithro
mumptai: In theory -- in practice it needs a lot of work
19:34
mithro
Bertl_oO: We can "stitch" together bitstreams from multiple sources
19:34
Bertl_oO
does that support relocation as well?
19:34
Bertl_oO
or how do I do that with e.g. DSPs?
19:35
Bertl_oO
(we do a lot of stuff in DSPs :)
19:36
mumptai
mithro, nice :-)
19:36
mithro
Need someone to do -- https://github.com/SymbiFlow/symbiflow-examples/issues/26
19:37
mithro
Bertl_oO: for the DSP stuff, we probably need to make that better
19:37
mithro
Bertl_oO: you can also use Yosys --> Vivado
19:38
Bertl_oO
does yosys do VHDL now?
19:39
mithro
https://github.com/enjoy-digital/litex/pull/551 -- Add Symbiflow toolchain support for Xilinx 7-series #551
19:39
Bertl_oO
ah yes, there seems to be a ghdl plugin ... but experimental
19:39
mithro
Bertl_oO: The j-core and microwatt people are using it pretty heavily it appears
19:40
Bertl_oO
definitely have to check that out
19:41
mumptai
i don't understand why the fsbl config has to be fuzzed, is the documentation so bad? or some legal reason?
19:42
mumptai
there is a lot of stuff to be configured, but most should be described in the reference? also everybody just uses the ps-init from the vivado projects
19:42
Bertl_oO
mithro: so what's the interface between yosys and vivado?
19:43
mithro
EDIF
19:43
Bertl_oO
but pre routing/placement?
19:45
mithro
Yes
19:45
mithro
http://j.mp/symbiflow-status-doc
19:47
Bertl_oO
so that is probably not a big advantage then
19:47
Bertl_oO
as synthesis is pretty fast in vivado
19:48
Bertl_oO
anyway, good to know that there is progress
20:15
mithro
Bertl_oO: getting your design goes into Yosys is the first step to using the open source toolchain
20:15
mithro
Also it lets you compare the open source PnR verse vivado
21:55
se6ast1an
off to bed
21:55
se6ast1an
good night
22:50
BAndiT1983
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23:09
mumptai
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schmoggie
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