Current Server Time: 07:16 (Central Europe)

#apertus IRC Channel Logs

2019/06/16

Timezone: UTC


01:12
RexOrCine
changed nick to: RexOrCine|away
02:58
apurvanandan[m]
Hi Bertl, I guess In out pipe is configurable by D3XX only. The ft601 controller is almost complete and is able to reach 385 MBps RX and 395 MBps TX. Only bug I see that when I restart the data transfer, some packets in starting are lost.
03:05
apurvanandan[m]
I am pushing the code on GitHub. So would you like to have a look at code :)
03:22
Bertl
sounds great!
03:24
Bertl
regarding configuration, IIRC there are libftdi commands to write one as well
03:25
apurvanandan[m]
Yes using d3xx , configuration is being written to the chip everytime
03:25
Bertl
but I'm not sure they work on FT60x
03:26
apurvanandan[m]
So is this good for final product?
03:26
Bertl
yes, for now we don't mind d3xx
03:26
futarisIRCcloud
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03:27
apurvanandan[m]
Ok, and I will see why I am losing starting data packets.
03:27
Bertl
data rates sound acceptable, the 'dropped packets' need investigation
03:27
apurvanandan[m]
Yup
03:27
Bertl
you also want to make sure that you are not losing packets during the transfer
03:28
apurvanandan[m]
Ok will check that using the program :)
04:38
Bertl
off to bed now ... have a good one everyone!
04:39
Bertl
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08:50
se6astian|away
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09:02
illwieckz
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09:38
BAndiT1983|away
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BAndiT1983
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futarisIRCcloud
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se6astian
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12:53
BAndiT1983|away
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illwieckz
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14:01
BAndiT1983
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14:14
BAndiT1983|away
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14:15
Bertl_zZ
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14:15
Bertl
morning folks!
14:16
BAndiT1983
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14:22
se6astian|away
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14:22
se6astian
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BAndiT1983|away
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se6astian|away
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se6astian
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se6astian|away
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14:48
se6astian
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se6astian|away
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14:55
BAndiT1983
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15:30
felix_
RexOrCine|away: ah, that's what this is called. thx :)
18:19
illwieckz
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illwieckz
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18:46
Nira|away
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19:40
danieel
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19:41
apurvanandan[m]
Hey Bertl , I checked and found that not a single packet is lost during the transfer or at starting of transfer. Some data is lost at the end of transfer when the D3XX stops the reading process.
19:42
apurvanandan[m]
I am formatting the code and will upload it.
19:42
Bertl
sounds great!
19:42
apurvanandan[m]
Bertl, Could help me on how to setup LVDS connections from my Virtex-5 fpga to the plugin module?
19:43
Bertl
sure
19:44
apurvanandan[m]
Currently I have removed the fifos from the code as the data generation is clocked by the ft601 clock.
19:44
apurvanandan[m]
I will add them when I do channel bonding code
19:56
anuejn_
apurvanandan[m]: what kind of software are you using on the pc side??
19:57
anuejn_
the proprietary libftdi or something that is open source?
19:57
apurvanandan[m]
D3xx software example
20:01
anuejn_
ah tx
20:03
apurvanandan[m]
np
21:10
BAndiT1983|away
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BAndiT1983
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21:40
comradekingu
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22:34
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23:01
se6astian
off to bed
23:01
se6astian
good night
23:01
se6astian
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23:20
illwieckz
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23:29
Nira
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23:37
danieel
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