Current Server Time: 17:18 (Central Europe)

#apertus IRC Channel Logs

2019/06/16

Timezone: UTC


00:12
RexOrCine
changed nick to: RexOrCine|away
01:58
apurvanandan[m]
Hi Bertl, I guess In out pipe is configurable by D3XX only. The ft601 controller is almost complete and is able to reach 385 MBps RX and 395 MBps TX. Only bug I see that when I restart the data transfer, some packets in starting are lost.
02:05
apurvanandan[m]
I am pushing the code on GitHub. So would you like to have a look at code :)
02:22
Bertl
sounds great!
02:24
Bertl
regarding configuration, IIRC there are libftdi commands to write one as well
02:25
apurvanandan[m]
Yes using d3xx , configuration is being written to the chip everytime
02:25
Bertl
but I'm not sure they work on FT60x
02:26
apurvanandan[m]
So is this good for final product?
02:26
Bertl
yes, for now we don't mind d3xx
02:26
futarisIRCcloud
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02:27
apurvanandan[m]
Ok, and I will see why I am losing starting data packets.
02:27
Bertl
data rates sound acceptable, the 'dropped packets' need investigation
02:27
apurvanandan[m]
Yup
02:27
Bertl
you also want to make sure that you are not losing packets during the transfer
02:28
apurvanandan[m]
Ok will check that using the program :)
03:38
Bertl
off to bed now ... have a good one everyone!
03:39
Bertl
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07:50
se6astian|away
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08:02
illwieckz
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BAndiT1983|away
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BAndiT1983
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futarisIRCcloud
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se6astian
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11:53
BAndiT1983|away
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12:44
illwieckz
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13:01
BAndiT1983
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13:14
BAndiT1983|away
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13:15
Bertl_zZ
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13:15
Bertl
morning folks!
13:16
BAndiT1983
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13:22
se6astian|away
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13:22
se6astian
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BAndiT1983|away
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se6astian|away
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se6astian
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se6astian|away
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se6astian
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se6astian|away
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13:55
BAndiT1983
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14:30
felix_
RexOrCine|away: ah, that's what this is called. thx :)
17:19
illwieckz
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17:46
Nira|away
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18:40
danieel
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18:41
apurvanandan[m]
Hey Bertl , I checked and found that not a single packet is lost during the transfer or at starting of transfer. Some data is lost at the end of transfer when the D3XX stops the reading process.
18:42
apurvanandan[m]
I am formatting the code and will upload it.
18:42
Bertl
sounds great!
18:42
apurvanandan[m]
Bertl, Could help me on how to setup LVDS connections from my Virtex-5 fpga to the plugin module?
18:43
Bertl
sure
18:44
apurvanandan[m]
Currently I have removed the fifos from the code as the data generation is clocked by the ft601 clock.
18:44
apurvanandan[m]
I will add them when I do channel bonding code
18:56
anuejn_
apurvanandan[m]: what kind of software are you using on the pc side??
18:57
anuejn_
the proprietary libftdi or something that is open source?
18:57
apurvanandan[m]
D3xx software example
19:01
anuejn_
ah tx
19:03
apurvanandan[m]
np
20:10
BAndiT1983|away
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20:22
BAndiT1983
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20:40
comradekingu
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21:34
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22:01
se6astian
off to bed
22:01
se6astian
good night
22:01
se6astian
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22:20
illwieckz
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22:29
Nira
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22:37
danieel
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