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#apertus IRC Channel Logs

2015/10/15

Timezone: UTC


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fsteinel
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01:53
mithro
FYI - https://www.crowdsupply.com/numato-lab/opsis/updates/1870 :)
01:55
Bertl
great work Mike did there, indeed!
01:58
Bertl
mithro: btw, was DP with 1.62Gb/s tested yet? That might be within the reach of non GT interfaces, at least for output
01:59
mithro
Bertl: No, I don't think it has been
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Bertl
off for a nap ... bbl
05:16
Bertl
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niemand
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se6astian|away
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07:05
se6astian
good morning
07:28
danieel
mornin
07:36
Bertl_zZ
changed nick to: Bertl
07:36
Bertl
back now ...
08:30
irieger
Morning folks. Was just interrupted two days ago when we talked about the FPGAs ...
08:30
irieger
Bertl: Hope feel better now?
08:32
irieger
Bertl, mithro: Had another look at the Opsis. Looks quite interesting. You guys think it could handle 3D LUTs in 4K or you think this would need more power than the Spartan-6 offers?
08:34
mithro
irieger: only way to know for sure is to try it
08:34
irieger
Bertl: What I wanted to ask on Tuesdays when we talked about the VHDL stuff: Is it possible to simulate the FPGA on the PC to mess with the processing code? (I assume it isn't that easy cause it would need a simulation of the IOs as well to simulate the processing I guess?
08:35
irieger
mithro: Go ahead ;-)
08:37
irieger
mithro: As a student I'm always a bit short on the money but I think about if I could get one to mess around with. And shipping in February would mean I most likely wouldn't get it while still writing my Bachelor thesis which would be good to not distract me ;-)
08:38
mithro
irieger: put together a spec and I'll get you an quote for Engineering hours :-) - otherwise happy to mentor someone who was interested
08:39
Bertl
irieger: there are a number of tools (ranging from free to _very_ expensive) to simulate FPGAs/VHDL
08:39
Bertl
and thanks, yes I'm feeling somewhat better ... i.e. situation is improving :)
08:39
irieger
mithro: When I win the lottery we can talk ..
08:39
irieger
Bertl: Good to hear.
08:41
irieger
Bertl: As I started to read into the VHDL stuff last week or so I already read that therer are different simulators. I just directly thought: Simulating the FPGA is the one thing. But it would need a simulation of the sensor input and a video out to really allow the simulation, wouldn't it?
08:41
mithro
irieger: You might want to take a look at something like migen
08:41
mithro
irieger: specially if you already know python
08:44
irieger
mithro: Looks interesting. This works efficiently? Sounds like a hard task to translate programmed code to a parallel running logic ...
08:45
Bertl
it's basically a macro language wrapper
08:45
mithro
irieger: you still have to write your code in parallel logic, it just in a higher level interface
08:45
mithro
irieger: do you understand the maths you actually want to do?
08:46
Bertl
the hard part of "mapping" programming to parallel logic happens on the tool/implementation side
08:48
irieger
mithro, Bertl: Ok, I get it. In the first moment the introduction text about migen looked a bit like too much magic without going deeper in the documentation/samples
08:48
irieger
mithro: sure, the logic is quite "simple" ...
08:49
mithro
irieger: can you write it up somewhere with some diagram / equations?
08:49
irieger
mithro: I think there should be stuff out there describing it. I just fired up google.
08:50
Bertl
3D Luts do 3 dimensional interpolation between (sometimes carefully) placed points
08:50
mxf_
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08:50
mxf_
Hello irc !
08:50
Bertl
the input is typically RGB (or XYZ) and the output is the same color space
08:51
mxf_
Live from Louis-Lumière in Paris
08:51
Bertl
mxf_: Hey Maxime!
08:52
irieger
mithro: http://spie.org/samples/PM159.pdf seems to cover the basics and different interpolation methods
08:54
Bertl
IIRC, somebody (who payed a visit here) did a PhD about 3D Luts in FPGAs, and the rough estimation was that 4k would require half the processing power of the Zynq for trilinear interpolation
08:55
irieger
Bertl: Ok, Thought it would take up quite some FPGA-Space ...
08:55
mithro
Bertl: which size Zynq?
08:55
Bertl
ah, sorry, the 7020
08:56
mithro
Bertl: Is this just a colorspace transform?
08:56
Bertl
yes
08:57
mithro
Each pixel input value has exactly one pixel value output?
08:57
Bertl
the complexity arises from the fact that typical devices have not enough space for a simple lookup table
08:57
Bertl
i.e. with 8 bit RGB:444 you have 24bit to look up and generate 24bit
08:58
Bertl
with 12 bit per channel, that becomes 36bit :)
08:58
Bertl
so, the solution is to make the ranges sparse
08:58
mithro
The Spartan-6 has 58 DSP slices which is 18bits wide
08:58
irieger
We could just attach a GeForce/Radeon at the camera back and use OpenCL/GL shaders ;-)
09:00
mithro
I wonder if they can be used for most of the effort
09:00
Bertl
yes, the interpolation part
09:00
Bertl
the problem is the high pixel clock at 4k, which requires parallelization and pipelining
09:01
mithro
Yeah
09:01
Bertl
also the values for interpolating need to be fetched from the actual lookup tables (memory blocks)
09:02
mithro
You would want to be doing probably 8 or 16 pixels at the same time
09:03
mithro
You are looking at a pixel clock of 340MHz - getting the design to operate at a clock of 50-75MHz seems pretty doable, which mean you might only need to do 4 pixels at the same time
09:04
mithro
If your tables were small enough to fit in the block ram - that should work too
09:06
mithro
sounds pretty doable, but these things are always tricky
09:06
Bertl
with careful pipelining and the help of those dsp blocks it should be doable, yes
09:07
irieger
Sounds cool.
09:07
mithro
Anything involving 4k is going to require careful use of the Spartan-6 specific features
09:07
Bertl
"only" for display port in/out for now (not SDI) but maybe opsis v2 will allow for that as well
09:08
Bertl
(hardware wise)
09:08
irieger
Yeah, but with the Dual Mode and fitting adapters it could at least handle HDMI 1.4/2.0 4K signals as far as I understand it
09:09
irieger
SDI would always be preferable as a connection but HDMI works too for most cases.
09:11
Bertl
have you found a reasonable HDMI to DP adapter yet?
09:13
irieger
Ok, I see now that most adapters specifically list DP->HDMI only
09:14
Bertl
just saying, but it might not be that a problem with the opsis
09:14
irieger
Yes. Maybe it's mostly a warning due to most DP-inputs not being Dual Mode able or something
09:23
irieger
Bertl: Is there a overview over the FPGA processing structure for the Axiom? Like showing the flow between the different entities or just roughly showing which parts of the design do what?
09:24
Bertl
https://wiki.apertus.org/index.php?title=Axiom_Alpha_Software#Image_Pipeline
09:25
Bertl
mxf_: so, did you succeed to get a snapshot yet?
09:25
irieger
Sure, I know this graphic. I mean a overview over the VHDL code to see which file(entity) contains what part of this processing
09:25
Bertl
not yet, feel free to create one though
09:25
Bertl
the entity names are quite descriptive IHMO
09:31
irieger
Bertl: Not there yet. The hardest hardware logics I had to deal with since now where small combinations of the basic and,nor,xor etc. in a very small scale with only a few gates. Stuff I did about 8 years ago in school. I can code you some advanced debayering code and color conversions on CUDA or so but for the VHDL part I have to get the right thinking first ;-)
09:38
cbohnens|away
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09:59
mxf_
Bertl_: not yet, we are discussing about the day's schedule !
10:00
Bertl
ah, yes, I forgot about the meetings and discussions :)
10:01
mxf_
Bertl_: first question though : do we have control over the analog to digital conversion in the sensor ?
10:01
Bertl
you have control of all the register the cmv12k offers
10:02
Bertl
I presume you've already studied the datasheet
10:05
mxf_
not yet...
10:06
Bertl
well, then I suggest you do that quickly but thoroughly, it's quite a number of registers
10:11
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11:25
mithro
irieger: it does appear that HDMI->DP dual mode adapters are harder to find that I had guess
11:25
mithro
irieger: which is really weird because they *are* actually passive adapters
11:27
Bertl
careful
11:27
Bertl
this is assuming that you are dealing with HDMI and have a dual role sink, which AFAIK is not really defined
11:53
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12:31
irieger
mithro: It is passive but needs another pin setup for the HDMI->DP directrion, right?
12:32
irieger
Bertl: Which HDMI-Modes does the Axiom currently support? Is 12 bit 444 supported?
12:33
Bertl
it supports whatever you can generate with ~1.5Gb/s bandwidth per lane
12:34
irieger
I have no clue how HDMI works. I mean what is already implemented?
12:34
Bertl
we currently do RGB:444 8bit
12:35
irieger
ok. You think 12bit are possible?
12:35
Bertl
requires twice the bandwidth, so will reduce resolution by half
12:37
Bertl
s/by/to/
12:37
irieger
Ok. That sucks.
12:38
Bertl
well, more data means more bandwidth
12:39
irieger
Thought with the sensor being 12 bit linear if I understand the datasheet right we could get a 12 bit out of the debayered data without any more processing done after staying linear for more rawish date (I know it's quite different to raw...).
12:40
Bertl
sure, we are just talking HDMI bandwidth here
12:40
Bertl
not related to the sensor at all
12:40
irieger
I know. But with plans for 1080p60 per HDMI port according to the Axiom specs I hoped that 1080p24 in 12 bit would be possible
12:40
Bertl
it should be, we have 1080p60 RGB:444 8bit running
12:40
irieger
Bertl: I know. Was just the idea why 12 bit RGB would be nice.
12:41
irieger
Ok. Who needs more ...
12:41
Bertl
so, 12 or even 16bit at 1080p30 should be doable
12:41
irieger
would wish direct M.2 SSD or something recording in the Gamma with up to 300fps at max 10 bit
12:42
irieger
I think I didn't wrote this idea here before?
12:42
Bertl
why 10bit if the sensor can do more?
12:43
irieger
Bertl: according to the specs it is 12 bit up to 132 fps and 300 fps at 10 bit
12:43
Bertl
yeah, but you wrote max 10 bit recording
12:43
irieger
Ok, when reading only a 16:9 area a few more frames could be possible using the X/Y subsampling
12:44
irieger
I meant max in regards to being the max bitdepth possible in full 4:3 300 fps readout
12:45
irieger
Would be killer to have one of the highest speed non-specialised HighSpeed cams with the Gamma. But cooling will be a major problem I assume. And needing more processing power/bandwith in the whole system possibly?
12:47
irieger
Have to go afk. (btw. should maybe look into proper handling of away states in my irssi ...)
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13:19
mxf_
hello back IRC =
13:19
mxf_
!
13:21
Bertl
wb mxf_!
13:25
mxf_
I didn't have time yet to figur out the ssh protocol
13:25
mxf_
so I'm trying to take pictures with the alpha via serial (putty) and then take them via ftp
13:26
Bertl
you are not serious are you?
13:26
mxf_
but when I type the code for displaying the image, it gives :
13:26
mxf_
http://webchat.freenode.net/?channels=apertus&uio=d4
13:26
mxf_
sorry
13:26
Bertl
this is a 10 second procedure to add your key
13:26
Bertl
you are on linux, yes?
13:26
mxf_
yes
13:27
Bertl
cat ~/.ssh/id_rsa.pub
13:27
mxf_
display.im6: no decode delegate for this image format `image.raw16' @ error/constitute.c/ReadImage/544.
13:27
Bertl
will output your ssh key (if you already have one) or complain that the file doesn't exist
13:27
mxf_
I'm doing the ssh key in the same time
13:28
Bertl
if it doesn't exist, run ssh-keygen
13:28
Bertl
on the Beta console, you do:
13:29
Bertl
cat >>~/.ssh/authorized_keys
13:29
Bertl
then you copy/paste the key there and press CTRL-D
13:30
Bertl
check with
13:30
Bertl
cat ~/.ssh/authorized_keys
13:30
Bertl
that it was correctly added
13:31
Bertl
and regarding display, you need to specify the raw format as in the example on the wiki
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13:33
Bertl
i.e. display -size 4096x3072 -depth 16 gray:image.raw16
13:39
mxf_
ok ! got it ! (for the display part)
13:39
mxf_
sorry I'm interrupted every 20 seconds !
13:40
Bertl
that gives you enough time for the ssh part :)
13:41
Bertl
(remember only takes 10 seconds):
14:01
mxf_
ok I'm on the ssh "part"
14:02
mxf_
I've written cat >>~/.ssh/authorized_keys and it's working for 40s now without giving back the hand
14:03
mxf_
(and how do I copy/paste my key from my computer to beta ?)
14:04
Bertl
with the mouse?
14:04
Bertl
it will not return until you copy/pasted the key and pressed CTRL-D
14:05
Bertl
is this the first time you are using linux?
14:12
niemand
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14:30
mxf_
not the first time using linux, but putty is not intuitive to me
14:30
Bertl
who uses putty on linux?
14:31
Bertl
linux has minicom, anyway ... did you manage to add your key?
14:31
mxf_
you recommand another serial emulator ?
14:31
Bertl
don't change it now, it seems to work for you
14:32
mxf_
no because I can't manage to use the clipboard with putty !
14:32
Bertl
I was just wondering because usually putty is used on windows
14:32
mxf_
(not working that much it seems )
14:32
Bertl
select the text with the mouse
14:32
Bertl
then move over to the console window (beta)
14:32
Bertl
and press the middle mouse button
14:35
mxf_
ok
14:36
mxf_
I did manage to paste (ctrl + shift + insert) and to add my key to the beta
14:36
Bertl
okay, does it work now? i.e. can you ssh in?
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mxf_
nop
14:51
Bertl
mxf_: please check private chat
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se6astian
gotta go
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Bertl
off for a nap ... bbl
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Bertl
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