#apertus IRC Channel Logs

great work Mike did there, indeed!

Bertl: No, I don't think it has been

good morning

Morning folks. Was just interrupted two days ago when we talked about the FPGAs ...

Bertl, mithro: Had another look at the Opsis. Looks quite interesting. You guys think it could handle 3D LUTs in 4K or you think this would need more power than the Spartan-6 offers?

Bertl: What I wanted to ask on Tuesdays when we talked about the VHDL stuff: Is it possible to simulate the FPGA on the PC to mess with the processing code? (I assume it isn't that easy cause it would need a simulation of the IOs as well to simulate the processing I guess?

mithro: As a student I'm always a bit short on the money but I think about if I could get one to mess around with. And shipping in February would mean I most likely wouldn't get it while still writing my Bachelor thesis which would be good to not distract me ;-)

irieger: there are a number of tools (ranging from free to _very_ expensive) to simulate FPGAs/VHDL

mithro: When I win the lottery we can talk ..

Bertl: As I started to read into the VHDL stuff last week or so I already read that therer are different simulators. I just directly thought: Simulating the FPGA is the one thing. But it would need a simulation of the sensor input and a video out to really allow the simulation, wouldn't it?

irieger: specially if you already know python

it's basically a macro language wrapper

irieger: do you understand the maths you actually want to do?

mithro, Bertl: Ok, I get it. In the first moment the introduction text about migen looked a bit like too much magic without going deeper in the documentation/samples

irieger: can you write it up somewhere with some diagram / equations?

3D Luts do 3 dimensional interpolation between (sometimes carefully) placed points

Hello irc !

Live from Louis-Lumière in Paris

mithro: http://spie.org/samples/PM159.pdf seems to cover the basics and different interpolation methods

Bertl: Ok, Thought it would take up quite some FPGA-Space ...

ah, sorry, the 7020

yes

the complexity arises from the fact that typical devices have not enough space for a simple lookup table

with 12 bit per channel, that becomes 36bit :)

The Spartan-6 has 58 DSP slices which is 18bits wide

I wonder if they can be used for most of the effort

the problem is the high pixel clock at 4k, which requires parallelization and pipelining

also the values for interpolating need to be fetched from the actual lookup tables (memory blocks)

You are looking at a pixel clock of 340MHz - getting the design to operate at a clock of 50-75MHz seems pretty doable, which mean you might only need to do 4 pixels at the same time

sounds pretty doable, but these things are always tricky

Sounds cool.

"only" for display port in/out for now (not SDI) but maybe opsis v2 will allow for that as well

Yeah, but with the Dual Mode and fitting adapters it could at least handle HDMI 1.4/2.0 4K signals as far as I understand it

have you found a reasonable HDMI to DP adapter yet?

just saying, but it might not be that a problem with the opsis

Bertl: Is there a overview over the FPGA processing structure for the Axiom? Like showing the flow between the different entities or just roughly showing which parts of the design do what?

mxf_: so, did you succeed to get a snapshot yet?

not yet, feel free to create one though

Bertl: Not there yet. The hardest hardware logics I had to deal with since now where small combinations of the basic and,nor,xor etc. in a very small scale with only a few gates. Stuff I did about 8 years ago in school. I can code you some advanced debayering code and color conversions on CUDA or so but for the VHDL part I have to get the right thinking first ;-)

Bertl_: not yet, we are discussing about the day's schedule !

Bertl_: first question though : do we have control over the analog to digital conversion in the sensor ?

I presume you've already studied the datasheet

well, then I suggest you do that quickly but thoroughly, it's quite a number of registers

irieger: it does appear that HDMI->DP dual mode adapters are harder to find that I had guess

careful

mithro: It is passive but needs another pin setup for the HDMI->DP directrion, right?

it supports whatever you can generate with ~1.5Gb/s bandwidth per lane

we currently do RGB:444 8bit

requires twice the bandwidth, so will reduce resolution by half

Ok. That sucks.

Thought with the sensor being 12 bit linear if I understand the datasheet right we could get a 12 bit out of the debayered data without any more processing done after staying linear for more rawish date (I know it's quite different to raw...).

not related to the sensor at all

it should be, we have 1080p60 RGB:444 8bit running

Ok. Who needs more ...

why 10bit if the sensor can do more?

yeah, but you wrote max 10 bit recording

I meant max in regards to being the max bitdepth possible in full 4:3 300 fps readout

Have to go afk. (btw. should maybe look into proper handling of away states in my irssi ...)

hello back IRC =

wb mxf_!

so I'm trying to take pictures with the alpha via serial (putty) and then take them via ftp

but when I type the code for displaying the image, it gives :

sorry

you are on linux, yes?

cat ~/.ssh/id_rsa.pub

will output your ssh key (if you already have one) or complain that the file doesn't exist

if it doesn't exist, run ssh-keygen

cat >>~/.ssh/authorized_keys

check with

that it was correctly added

ok ! got it ! (for the display part)

that gives you enough time for the ssh part :)

ok I'm on the ssh "part"

(and how do I copy/paste my key from my computer to beta ?)

it will not return until you copy/pasted the key and pressed CTRL-D

who uses putty on linux?

you recommand another serial emulator ?

no because I can't manage to use the clipboard with putty !

(not working that much it seems )

then move over to the console window (beta)

ok

okay, does it work now? i.e. can you ssh in?

nop

gotta go