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#apertus IRC Channel Logs

2019/07/15

Timezone: UTC


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05:48
Bertl
off to bed now ... have a good one everyone!
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Bertl
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12:02
se6astian
I need to shutdown the remote access beta for a bit, anyone doing anything on it currently?
12:52
se6astian
and its reinstalled again and operational
12:53
aSobhy
Ok thanks :)
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Bertl_zZ
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14:32
Bertl
morning folks!
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Bertl
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dev__
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16:57
apurvanandan[m]
Hi Bertl
16:57
BAndiT1983
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16:59
apurvanandan[m]
I am having problem in syncing the PRNGs, I am stuck in it :/
17:00
BAndiT1983|away
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17:01
Bertl_oO
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17:02
Bertl
meeting time
17:02
apurvanandan[m]
okay
17:03
se6astian|away
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17:03
dev__
Good evening everyone
17:03
se6astian
good evening
17:03
se6astian
sorry for the delay
17:03
se6astian
meeting time!
17:03
Fares
Good evening
17:03
se6astian
again please pm me and then we will start the reporting sessions
17:06
se6astian
Fares you start please
17:06
Fares
Hi everyone! sorry I missed last week meeting
17:07
Fares
In the last two weeks I almost completed the documentation for all the files and few high level documentation
17:08
Fares
I finished a module to append a marker to start/end of each frame and completed an axi lite module for the dma
17:08
Fares
I also completed fifo, simple address generator and bit conversions module for the axihp_reader|writer
17:09
Bertl
sounds great! any hardware tests yet?
17:10
se6astian
is the documentation already on github? I didnt see anything on the wiki yet
17:10
Fares
for all the things but the dma is working, for the dma I managed to get around 240 correct bytes, there was a bug in the wlast, after fixing it, the zynq freezes after the dma starting, I'm still tryin to figure out why
17:11
Fares
the documentation is technical and describe what every module does in the encoding process
17:11
Fares
I didn't know about the wiki, but I would gladly document it in more high level there.
17:12
se6astian
where is the documentation going to be hosted you wrote so far?
17:12
Fares
github
17:12
dev__
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17:13
se6astian
great, for technical documentation github and right with the project files is perfect
17:13
se6astian
high level documentation and general overview with links to further content (code, documentation, usage examples, et.) on the wiki would be great
17:14
dev__
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17:14
Fares
great! that was everything I was working on last two weeks, I want to schedule a suitable time with you to present the LJ92 algorithm and describe how the core is working in high level and also to determine which modules will be in the final version, as I need time before GSoC deadline to write supporting software.
17:15
se6astian
great
17:15
se6astian
lets discuss that presentation time afterwards
17:15
se6astian
thanks Fares
17:15
Fares
great, thank you.
17:15
se6astian
Y_G your turn
17:16
Y_G
Hi all,
17:16
Y_G
This week I worked on and tested splitting the message package in 2 parts (Blob, String Parameter).
17:17
Y_G
Worked on LutConfModule which uses the Blob Packet to set gamma_correction_lut's.( Though the file format has not been decided for LUT file ,Currently I have assumed it to be 4096*4 values.)
17:17
BAndiT1983
4096 * 8bit or 16bit?
17:18
se6astian
what are "values" for you?
17:19
Y_G
float values ,Just took those values that are generated by the formula currently in lut_conf.c when set_gain is called
17:19
BAndiT1983
are LUT values really float?
17:20
Bertl
the lut values are 16/18bit integers
17:20
Y_G
The ones generated using the formula were'nt
17:20
Bertl
they are calculated as floats but they are written into the LUT tables as integers
17:20
Dev_
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17:21
Y_G
But some files I looked up had float values. So for testing purposes I used float
17:21
Y_G
Shouldn't be a problem for int values too
17:22
BAndiT1983
i would mostly avoid float on the camera, if possible
17:22
Bertl
I think it is important to differentiate between values stored in files and the values set in LUT registers
17:22
Bertl
it makes perfect sense to store normalized LUT values in files
17:22
Bertl
i.e. floats between 0.0 and 1.0
17:22
dev__
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17:24
Y_G
How do we interpret these values (0.0 to 1.0) for register settings ?
17:24
Bertl
well, that really depends on the LUT and how it is used
17:25
Bertl
i.e. if the LUT has 16bit, you want to spread the 0-1 interval to the full 16bit range
17:26
se6astian
anything else to report Y_G otherwise I would suggest to discuss the last remaining questions about the LUT value calculation after the meeting
17:27
Y_G
I also finally worked on setting and getting i2c values directly through DaemonCLI (This has to be tested in Beta.)
17:27
Y_G
Should be able to test it today only
17:28
Y_G
That would be it from my side .thanks
17:28
se6astian
good, the remote beta should be fully operational and waiting for you :)
17:28
se6astian
great, thanks for the update
17:28
se6astian
Nira you are up next
17:28
Nira
ok, thank you
17:29
Nira
this week I have been doing the final debouncing test for the PIC16
17:29
Nira
I have done it for one button, so now it has to be 'extended' to work on all of them
17:29
Bertl
how did you test?
17:31
Nira
well, I have tested it on the remote, so checking that the leds did what I expected
17:31
Bertl
okay, what exactly did you test?
17:33
Nira
as I have two leds I used one of them to show if it has detected 'for real' that the button has been pushed, and the other one for 'fake' pulses
17:34
Nira
and well, it worked for pushing the button, and it didn't detect any fake
17:35
Bertl
which means the button just didn't bounce at all, no?
17:35
Bertl
anyway, we should discuss that later as well, please continue
17:36
Nira
this would be all
17:37
se6astian
thanks nira, further debouncing should indeed be discussed right after the meeting concludes
17:37
se6astian
Dev_: your turn
17:37
Dev_
hello Everyone
17:37
Dev_
last week, I spent most of the time in understanding of task for making an eventbus and event driven architechture for OC which will be used by frameserver
17:38
Dev_
Then, I fixed some problems regrading loading of DNG
17:38
Dev_
which occured
17:38
Dev_
due to working on addtional feture
17:38
Dev_
Form yesterday, i was working on VideoClip class and it is almost complete. Inclusion of videoclip class has reduced many responsiblity and unnecessary function from static allocator
17:38
Dev_
next week, i will be working on the implementation of eventbus for OC. If this completes next week, I guess, we can go for Fuse then.
17:39
BAndiT1983
??
17:39
BAndiT1983
This is totally behind the plan and timeline, i would have expected fuse playback at latest by the end of the week
17:40
Dev_
Yes BAndiT1983, I know
17:40
BAndiT1983
event bus is available in core, so i don't understand why you want to implement it again
17:40
BAndiT1983
https://github.com/apertus-open-source-cinema/opencine/tree/dev/Source/OCcore/Events
17:40
BAndiT1983
for basic things this implementation is sufficient
17:41
Dev_
Okay , I will work on it
17:42
se6astian
I suggest to also discuss the detailed next steps right after the meeting as there seems to be some discrepancy between planned and actual progress
17:42
Dev_
After Eventbus in working state , we can go for fuse
17:42
Dev_
okay, I will be here
17:42
se6astian
thanks Dev_, anything else?
17:43
Dev_
No , That's it
17:43
se6astian
great
17:43
se6astian
aSobhy: your turn
17:44
aSobhy
hi all
17:44
aSobhy
the past week i have finished (coding) the link training for both side with word alignment
17:44
aSobhy
simulating the Machxo2 side right now
17:45
aSobhy
will simulate both together after the meeting and run them on the Beta tonight or tomorrow at most
17:45
Bertl
okay, please keep me updated
17:45
aSobhy
there were some troubles i faced: the encoding 8b/10b is running alone fine but with the other modules doesn't work
17:46
aSobhy
I left it for now and will find another 8b/10b open source code to see if my code that had the problem or not
17:47
aSobhy
sure Bertl :)
17:48
se6astian
thanks, anything else?
17:48
aSobhy
that's all ,thanks :)
17:49
se6astian
great
17:49
se6astian
anyone else want to give any updates?
17:49
se6astian
felix_: ?
17:49
apurvanandan[m]
I want to give my update
17:50
se6astian
great!
17:50
se6astian
please do
17:50
apurvanandan[m]
Hi everybody
17:50
se6astian
did you pm me and my irc bouncer swallowed it?
17:50
apurvanandan[m]
I had pm you
17:51
felix_
doesn't have anything new to tell
17:52
apurvanandan[m]
After I had successfully completed the BER testing model on post route simulation, I worked of finding the BER on harware ie real BER. I had to debug a lot on the hardware even if everything was perfectly working on post simulation and for debugging I had only one LED. But this is what I have achieved: Every thing is working good on hardware except that I am not able to synchronise the PRNGs so BER is coming to be
17:52
se6astian
apurvanandan[m]: right got it, please go ahead
17:52
apurvanandan[m]
50% but in case of counter the BER is remains constant that means it is definitely less than 10^-9. Once I am able to synchronise the PRNG I would then decrease the updates rates so that I can test for lower BER.
17:53
apurvanandan[m]
Thats all I had for this week.
17:54
Bertl
well, 50% sounds nice, how did you output the counter values?
17:55
apurvanandan[m]
Well for the counter I just replaced the prng lfsr with a 8 bit counter. In that case the BER takes a fixed value and doesn't change at all after that.
17:57
Bertl
doesn't really answer my question though :)
17:58
apurvanandan[m]
I didn't get your question, can you elaborate a bit?
17:58
Bertl
you said, you 'measured' a BER of 50%
17:58
Bertl
this means that half of the bits were wrong, the other half correct
17:59
Bertl
this requires that you did count the wrong bits somehow and also that you did read out that value in some way
17:59
Bertl
I was curious how you did that
18:00
apurvanandan[m]
ahh sorry, I measured it by sending it to my laptop by the ft601q
18:00
Bertl
okay, thanks!
18:00
apurvanandan[m]
It gets updated after counting everytime 2^28 bits ,
18:00
apurvanandan[m]
Yes thank you everybody!
18:01
se6astian
great, anything else to add?
18:02
apurvanandan[m]
No, I am done!
18:02
se6astian
thanks!
18:02
se6astian
quick updates from me: several AXIOM Beta CP enclosure related fine tuning going on currently
18:02
se6astian
we scheduled the next team talk video shooting for next week
18:02
se6astian
the 25th
18:03
se6astian
we have been accepted to do a booth at maker faire hannover in august
18:04
se6astian
thats it from my side, any closing words Bertl?
18:04
Bertl
nothing relevant to report from my side
18:04
Bertl
second evalutaion is coming, so be productive!
18:05
se6astian
right, then thanks everyone for attending again! meeting concluded, please discuss the things with your mentors now that we previously mentioned
18:07
Bertl
thanks for the moderation!
18:07
se6astian
my pleasure, I am off for dinner now, fares can we schedule the presentation a bit later or alternatively via email?
18:08
Bertl
apurvanandan[m]: regarding PRNG synchronization, IIRC we discussed that the 'forbidden' code can be used to do that
18:08
Fares
sure
18:09
Bertl
i.e. if your LFSR generates everything but a zero code, you can use this as sync code
18:09
Dev_
BAndiT1983, I would start working on eventbus (extend) from today itself , Then I can go for Fuse also in next of half of week
18:09
Bertl
and whenever the receiver detects a sync code, it simply resets the PRNG
18:09
Dev_
The videoClip class is also ready, I will push changes today
18:09
Bertl
(probably a good idea to add a counter for that as well for debugging)
18:10
apurvanandan[m]
Ealier I was using the switch from control codes to non control codes for syncing but it didn't seem to do well, so now I am changing to all zeroes method.
18:11
apurvanandan[m]
Bertl Is the conclusion I derived from constant BER reasonable?
18:12
Bertl
what do you mean with 'constant BER'?
18:13
apurvanandan[m]
If I used counter in place of LFSR, the BER I would recieve remains constant over time
18:14
apurvanandan[m]
That means the problem is PRNGs aren't synced right?
18:14
Bertl
a counter vs. a PRNG should give you the same as PRNG vs unsynchronized PRNG
18:14
Bertl
i.e. about 50% (half of all transmitted bits) would be wrong
18:15
BAndiT1983
Dev_: i would schedule next meeting for Wednesday, as progress is not up to my expectation
18:16
Dev_
Okay ,
18:16
Dev_
i will Email timmings
18:17
apurvanandan[m]
By constant I mean, the reported bit errors are exactly equal. In case of PRNG they are slightly varying but still very close to 50%
18:17
BAndiT1983
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18:18
apurvanandan[m]
But anyways, syncing only seems a possible issue.
18:18
Dev_
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18:19
Bertl
yeah, that's what you'd expect from unsynchronized PRNGs
18:19
Bertl
for a test, you can use a sideband signal for the synchronization
18:19
apurvanandan[m]
sideband?
18:19
Bertl
i.e. an unused LVDS pair which just 'resets' the PRNG
18:20
apurvanandan[m]
Yeah, also a good method
18:21
apurvanandan[m]
Apart from that, should I use asynchornous dual clock FIFO for linking the ft601 with the data?
18:27
Bertl
if you have two clocks, probably yes
18:27
apurvanandan[m]
Okay
18:27
Bertl
if you are clocking your data with the FT60x clock, there is no need to do that
18:28
se6astian
Fares: you still here, I am back
18:29
Fares
Yes, I'm here
18:29
se6astian
great, when did you have in mind for the presentation?
18:29
apurvanandan[m]
Also I have some confusion between DRR x2 and x4, they are the same on input side ie simple DDR but the DDR x4 forms eight bit words from it while DDR x2 forms 4 bit words right?
18:30
Fares
anytime today or in the following days would be good
18:30
Bertl
you are referring to the MachXO2 hardened IP?
18:32
se6astian
I will leave soon today for a bit and have appointments tomorro evening, what about wednesday evening?
18:34
Fares
okay sounds good, is that good with Bertl?
18:35
Bertl
wednesday evening should be fine, yes
18:36
apurvanandan[m]
Yes Bertl, the problem is the max frequency DDRX4 IP allows is 378MHz which is less than what I require
18:36
se6astian
great, 17:00 UTC?
18:36
se6astian
thats 36 minutes ago in 2 days
18:36
apurvanandan[m]
So I am currently testing it at 300 MHz as of now.
18:37
RexOrMatrix[m]
Well done and thanks for the updates everyone.
18:38
apurvanandan[m]
Bertl ie I can attain max of 3.0 MBps even if I clock at 378MHz, is this fine?
18:40
Bertl
why 3Mbit/s ?
18:41
Bertl
at 300MHz, with DDR x2 you should get 600Mbit/s or with DDR x4 twice as much :)
18:41
apurvanandan[m]
No I am getting 600MBits with DDR X4 at 300 MHz
18:43
Bertl
how's that?
18:43
apurvanandan[m]
How can the speed change, if the sampling scheme is same in both case which is DDR?
18:44
se6astian
Fares: , Bertl wednesday 17:00 UTC is confirmed?
18:45
apurvanandan[m]
Does not the DDR X4 means you are just grouping the signal in chunks of 8 bits like you do grouping of 4 in DDR X2?
18:45
Bertl
DDR is double data rate, i.e. it means that data is sampled at both the rising and falling clock edge
18:45
Bertl
so, 100MHz means 2 bit per clock cycle on DDR
18:45
Bertl
or a datarate of 200MBit/s
18:46
Bertl
DDR x2 and DDR x4 increase the gear ratio accordingly
18:46
Fares
se6adtian: That would be great with me
18:46
Fares
se6astian*
18:47
se6astian
perfect, appointment added to calendar
18:48
Bertl
apurvanandan[m]: but you are likely to hit a limit on the clock there
18:48
apurvanandan[m]
Right Bertl that means 600MBps x 5 channels x 0.8 ( due to encoding) = 2.4Gbps
18:48
Bertl
i.e. while your gear ratio can be 1:8, your clock cannot
18:51
Fares
Bertl: can you please provide me with any hints why would the axihp_reader|writer freeze the zynq? I assume the problem is writing to places in memory I should not write to?
18:51
Bertl
either that or any protocol error
18:52
Bertl
i.e. when you run out of addresses or similar
18:53
apurvanandan[m]
Bertl Is there a clock limit in the fpga fabric?
18:54
Bertl
definitely
18:55
apurvanandan[m]
So 378MHz won't be above that I guess
18:55
Bertl
unlikely
18:56
Bertl
but you can easily start testing at 100MHz
18:56
Bertl
and see that you get it working there, then slowly increase up till the maximum
18:57
apurvanandan[m]
I am currently testing everything at 300 MHz
18:57
apurvanandan[m]
And I think it is working fine as of now
18:57
Bertl
good then
18:58
Bertl
sorry, have to leave ... off for now ... bbl
18:58
Bertl
changed nick to: Bertl_oO
18:58
apurvanandan[m]
Ok bye
18:58
apurvanandan[m]
Np
19:02
Nira
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19:14
Y_G
That would be it from my side .thank
19:28
BAndiT1983|away
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BAndiT1983|away
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BAndiT1983
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21:03
se6astian
off to bed, good night
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se6astian
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BAndiT1983
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Nira|away
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