Current Server Time: 09:18 (Central Europe)

#apertus IRC Channel Logs

2018/07/15

Timezone: UTC

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BogdanXOR
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comradekingu1
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comradekingu
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06:04
Bertl_oO
davidak[m]: tx
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06:04
Bertl_oO
off to bed now ... have a good one everyone!
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06:04
Bertl_oO
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BogdanXOR
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ymc98_2
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BogdanXOR
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ymc98_1
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rton
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BogdanXOR
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09:39
BogdanXOR
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10:17
felix_
i wonder though why they chose to route the pcie x4 to a dual row 0.1" (or 0.05"?) connector. signal integrity says please don't ;) pcie is quite robust though, so it prbably ends up working
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BogdanXOR
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BogdanXOR
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BogdanXOR
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BogdanXOR
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LordVan
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jucar
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13:20
Bertl_zZ
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13:20
Bertl
morning folks!
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BogdanXOR
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jucar
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Robin_
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Robin_
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BogdanXOR
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15:14
BAndiT1983|away
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BogdanXOR
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BogdanXOR
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LordVan
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LordVan
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17:38
se6astian|away
changed nick to: se6astian
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illwieckz
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illwieckz
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illwieckz_
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illwieckz
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illwieckz_
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BogdanXOR
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BogdanXOR
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LordVan
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20:31
felix_
http://gerblook.org/pcb/s4L8MhjxyP6RkgcEZbgxGT :)
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21:03
se6astian
great!
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21:03
BAndiT1983
changed nick to: BAndiT1983|away
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21:03
BAndiT1983|away
changed nick to: BAndiT1983
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21:03
se6astian
do you think there is still some space to save and making the module slightly shorter?
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21:03
felix_
not really
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21:04
felix_
well, maybe 2mm shorter, but i really doubt that it's worth the hassle
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21:06
felix_
between the axiom high speed connector and the fpga there's no room left; between the sdi chips and the fpga is a little room left and between the hdbnc connectors and the sdi chips is also a little room
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21:06
se6astian
right
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21:07
felix_
i already moved the parts where's still a little room closer together
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21:08
felix_
when moving the sdi chips closer to the fpga we might get some crosstalk issues there
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21:09
se6astian
off to bed for today
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21:09
felix_
the displayport++ output module will likely get a bit shorter though
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21:09
felix_
good night
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21:09
se6astian
good night
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21:09
se6astian
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BAndiT1983
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BogdanXOR
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BogdanXOR
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jucar
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