#apertus IRC Channel Logs

Can everyone retweet https://twitter.com/TimVideosUs/status/841833734747774977 ?

Two ticks

mithro *

Yeah, country.

Your optimum time for tweeting is around 3pm to 5pm CET, or 4pm to 6pm GMT. 21% or GSoC students are from the US, and the other 21% India, so these are the timezones you wanna be catching. If you tweet again tomorrow at these time I'll reshare again. Copy @apertususer in if you want no worries.

RexOrCine: how do you figure this out / know about this?

morning folks!

Clock: BANK13_SE_0 [V5] to PT17A [88]

and for the east side routing fabric:

JX1_05_N/P [R14/P14] to PB11B/A [35,34]

is this interessting? : http://www.adapteva.com/announcements/an-open-source-8gbps-low-latency-chip-to-chip-interface/

github code link is broken for that

right link -> https://github.com/parallella/oh/blob/master/src/elink/README.md

but in case you want to do that for testing, the simplest way is to use one of the EMIO pins which are available in the PL fabric and can be controlled from the PS

the elink interface is quite old and uses a wide bus IIRC, so not too interesting for our cases

wb ArrunM! check the IRC logs for the pin information :)

4 bit crc and 5 bit divisor for 32 bit packet is fine?

nice, maybe link it on the lab task (if permitted)

mainly because the toolchain is not able to generate netlists and bitstreams which can be inserted in an existing slot (if you don't build everything at once)

or is this done just at start?

exchangeable filters or similar, jsut thinking about hdmi settings at the moment

basically all kind of functionality can be based on a reconfigureable design

input pipeline, processing, output pipeline

we are not using partial reconfiguration at the moment

Bertl, I have done an initial writeup on the component selection and determining open loop gain equation of the buck converter. The next steps would be to fine tune the parameters based on Bode plots, develop flow diagram in terms of Verilog modules and discuss the mixed mode simulation.

you'll have to wait a bit, he has gone to sleep some time ago

He's either gone to sleep or he's out on his skateboard.

usmankhan: nice writeup, a few comments here:

it might also be worth to drop the ADC in favor of one or maybe two comparators, as we already need a DAC to generate the reference voltage (i.e. the one the switcher will follow)

please let me know what you think and what 'solutions' you have in mind

currently i'm looking at CMV routines in scripts

you mean register map for the AXIOM Beta mappings?

i see 4 addresses in the script, but i can only guess what the are for -> https://github.com/apertus-open-source-cinema/beta-software/blob/master/beta-scripts/cmv.func

ah, very good, thanks

RexOrCine: really depends on the resolution

Full res?

(software limit)\

And*

note that this was not tested yet AFAIK

what is the real resolution after all, as there is some area for calibration usually? and which software limit?

(details in the sensor datasheet)

i have the sheet open, as i talked to se6astian about CMV registers before

the sensor can do up to 600MHz (for version 2, 300Mhz for version 1 sensors) but we only use around 200-240MHz currently

once we build a 'smart' interface board, we can also double the datarate, as we are currently only using 32 of the 64 data pairs

OTOH, the bandwidth to the DDR memory is also limited (we do not know the details yet as we didn't run extensive tests)

note that we also do not transfer data during exposure

so currently for 25 FPS, the 40ms per frame will be split into roughly 25ms transfer and 15ms exposure

I don't understand the question regarding global shutter limits

you mean dedicated two port memory or so?

i don't know how you call it in electronics, for me it's like cache

when the sensel voltages are 'copied' into the back store

the Microzed features 1GB of DDR3 SDRAM

https://www.micron.com/parts/dram/ddr3-sdram/mt41k256m16ha-125

they form an x32 bus with typically 533MHz clock IIRC

datasheet says 132 fps in that mode

that is the limitation from the sensor side at max clock rate and 64bit outputs

not bad

(according to the Cmosis datasheet that is :)

off to bed

which settings of CMV the user is/should be allowed to access?

allowed should be any of the registers

often a 'simple' setting will affect a bunch of registers which need to be set correctly to make it work

currently gain requires gain value of course and ADC range

I think there are two approaches to this:

can be done by bit fields

which do exactly that and provide a generic interface to the outside

at least it's the plan, to not reinvent the wheel i would "methodize" devmem, as it has almost no methods and all is done in main()

devmem is just the file interface to the kernel memory map