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#apertus IRC Channel Logs

2017/03/15

Timezone: UTC


23:21
arpu
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01:13
mithro
Can everyone retweet https://twitter.com/TimVideosUs/status/841833734747774977 ?
01:16
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01:30
RexOrCine
Two ticks
01:31
RexOrCine
Where are you Mithro?
01:31
RexOrCine
mithro *
01:32
mithro
RexOrCine: hrm? Physically?
01:32
RexOrCine
Yeah, country.
01:32
mithro
Australia, why?
01:34
RexOrCine
Your optimum time for tweeting is around 3pm to 5pm CET, or 4pm to 6pm GMT. 21% or GSoC students are from the US, and the other 21% India, so these are the timezones you wanna be catching. If you tweet again tomorrow at these time I'll reshare again. Copy @apertususer in if you want no worries.
01:34
RexOrCine
21% of *
01:43
mithro
RexOrCine: how do you figure this out / know about this?
01:49
RexO
The time zones? I'm well versed in traffic and numbers.
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BAndiT1983|away
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BAndiT1983
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07:48
mithro
Yay! Bunnie tweeted about us - https://twitter.com/bunniestudios/status/841912749479366657
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sagnikbasu95
Hi Bertl_zZ..are you busy now ?
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BAndiT1983|away
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BAndiT1983|away
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intracube
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15:22
Bertl_zZ
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15:22
Bertl
morning folks!
15:25
Elbehery
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15:28
Bertl
ArrunM: for the west side routing fabric, the pins are
15:29
Bertl
Clock: BANK13_SE_0 [V5] to PT17A [88]
15:30
Bertl
LVDS: BANK13_01_N/P [U10,T9] to PB16A/B [38,39]
15:30
Bertl
and for the east side routing fabric:
15:32
Bertl
Clock: JX1_SE_0 [R19] to PT17A [88]
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jucar
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15:33
Bertl
LVDS: JX1_04_N/P [T15/T14] to PB16A/B [38,39] and
15:34
Bertl
JX1_05_N/P [R14/P14] to PB11B/A [35,34]
15:42
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sagnikbasu
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15:46
sagnikbasu
Bertl : so the other day you were telling how the sobel filter will be on either the input or output of pipeline..so is there any kind of interface which when pressed by the user will send a interrupt kind of service ? I mean I am thinking of using a mux for this purpose
15:48
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derWalter
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15:48
derWalter
is this interessting? : http://www.adapteva.com/announcements/an-open-source-8gbps-low-latency-chip-to-chip-interface/
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15:49
BAndiT1983
github code link is broken for that
15:50
sagnikbasu
or develop a finite state machine
15:51
BAndiT1983
right link -> https://github.com/parallella/oh/blob/master/src/elink/README.md
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intracube_afk
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16:09
Bertl
sagnikbasu: I don't understand the interrupt thing, but if you plan to make the filter optional, then this is probably not required (at least not as part of the filter)
16:10
Bertl
but in case you want to do that for testing, the simplest way is to use one of the EMIO pins which are available in the PL fabric and can be controlled from the PS
16:14
BAndiT1983
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16:16
Bertl
the elink interface is quite old and uses a wide bus IIRC, so not too interesting for our cases
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16:18
Bertl
wb ArrunM! check the IRC logs for the pin information :)
16:18
ArrunM
thanks Got it.
16:20
ArrunM
4 bit crc and 5 bit divisor for 32 bit packet is fine?
16:21
Bertl
don't know, we have not done any tests yet regarding link quality
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16:33
sagnikbasu
bertl : ok..got it.BTW , check this journal https://www.hindawi.com/journals/js/2016/2654059/ . They implemented on a 1080p video
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16:49
Bertl
nice, maybe link it on the lab task (if permitted)
16:50
Bertl
dynamic reconfiguration is something we already considered for 'user filters' but while it works nicely in special cases, it is not that practical for a plug-in system
16:51
Bertl
mainly because the toolchain is not able to generate netlists and bitstreams which can be inserted in an existing slot (if you don't build everything at once)
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se6astian|away
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BAndiT1983|away
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17:54
BAndiT1983
Bertl, which parts are considered for live reconfiguration on FPGAs?
17:54
BAndiT1983
or is this done just at start?
18:05
Bertl
define 'parts'
18:06
BAndiT1983
exchangeable filters or similar, jsut thinking about hdmi settings at the moment
18:06
BAndiT1983
but there are much more possible things
18:12
Bertl
basically all kind of functionality can be based on a reconfigureable design
18:12
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18:12
Bertl
input pipeline, processing, output pipeline
18:13
BAndiT1983
xilinx says, that parts which are related to reconfigured area should be shut down first etc., so i was wondering what beta is using at the moment or, at least, what is planned
18:13
Bertl
we are not using partial reconfiguration at the moment
18:14
Bertl
there are plans for smart reconfiguration in the future\
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18:40
Bertl
off for now ... bbl
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Bertl
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19:25
usmankhan
Hello!
19:28
usmankhan
Bertl, I have done an initial writeup on the component selection and determining open loop gain equation of the buck converter. The next steps would be to fine tune the parameters based on Bode plots, develop flow diagram in terms of Verilog modules and discuss the mixed mode simulation.
19:29
usmankhan
Here it is: https://github.com/usmanwardag/gsoc17_proposal/blob/master/pid.pdf. I would appreciate if you can give any comments
19:29
BAndiT1983
you'll have to wait a bit, he has gone to sleep some time ago
19:29
usmankhan
Sure, no problem
19:35
RexO
He's either gone to sleep or he's out on his skateboard.
19:36
BAndiT1983
nah, not in the moonlight, moon burn could be the cause
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Bertl_oO
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21:36
Bertl
back now .,..
21:38
Bertl
usmankhan: nice writeup, a few comments here:
21:41
Bertl
the voltage range of the buck should at least be 1.5V - 3.6V ... with a spike current of up to 2A, so I think your LIR and inductor current will be higher
21:43
Bertl
it might also be worth to drop the ADC in favor of one or maybe two comparators, as we already need a DAC to generate the reference voltage (i.e. the one the switcher will follow)
21:45
Bertl
note that I don't see a problem with the ADC and I know that it provides better input for a regulation loop, but it is likely to complicate the 'follow' part
21:47
Bertl
please let me know what you think and what 'solutions' you have in mind
21:55
BAndiT1983
Bertl, is there a list of memory-mapped devices of the beta?
21:55
BAndiT1983
currently i'm looking at CMV routines in scripts
21:56
RexOrCine
Bertl What is the maximum number of frames beta can record continuously right now in burst mode?
21:56
Bertl
you mean register map for the AXIOM Beta mappings?
21:56
BAndiT1983
yes, like CMV etc.
21:58
BAndiT1983
i see 4 addresses in the script, but i can only guess what the are for -> https://github.com/apertus-open-source-cinema/beta-software/blob/master/beta-scripts/cmv.func
21:58
Bertl
https://wiki.apertus.org/index.php/CMV12000_Register_Blocks
21:58
BAndiT1983
ah, very good, thanks
21:58
Bertl
note that it is probably somewhat outdated though
21:59
Bertl
RexOrCine: really depends on the resolution
21:59
BAndiT1983
doesn't matter, as it should be reconfigurable easily
21:59
RexOrCine
Full res?
21:59
Bertl
at 4096x3072 the upper limit is around 40 FPS at the moment
22:00
Bertl
(software limit)\
22:00
RexOrCine
Any maybe 1080p as well because this is what most people are primarily concerned about I think.
22:01
RexOrCine
And*
22:01
Bertl
if you actually limit the vertical size to 1080 lines and maybe use binning in both directions, then you should be able to get four times as much, so between 140-150 FPS
22:02
Bertl
note that this was not tested yet AFAIK
22:02
RexOrCine
Many thanks.
22:02
BAndiT1983
what is the real resolution after all, as there is some area for calibration usually? and which software limit?
22:03
Bertl
the 'real' resolution is 4096x3072, but you can 'reserve' a number of black columns on the sides
22:03
Bertl
(details in the sensor datasheet)
22:03
BAndiT1983
ah, so canon just reduces the resolution
22:03
BAndiT1983
i have the sheet open, as i talked to se6astian about CMV registers before
22:03
Bertl
the 'software' limits are currently the transfer rate between sensor and FPGA as well as the memory interface
22:04
Bertl
the sensor can do up to 600MHz (for version 2, 300Mhz for version 1 sensors) but we only use around 200-240MHz currently
22:05
BAndiT1983
is fast enough already, is there some limitation to global shutter mode?
22:06
Bertl
once we build a 'smart' interface board, we can also double the datarate, as we are currently only using 32 of the 64 data pairs
22:06
Bertl
(that is a hardware limitation we have)
22:06
Bertl
OTOH, the bandwidth to the DDR memory is also limited (we do not know the details yet as we didn't run extensive tests)
22:07
BAndiT1983
which ddr type is used?
22:07
Bertl
note that we also do not transfer data during exposure
22:07
BAndiT1983
what is the reason?
22:08
Bertl
so currently for 25 FPS, the 40ms per frame will be split into roughly 25ms transfer and 15ms exposure
22:09
Bertl
the reason is that we know that concurrent readout reduces the quality and needs to be compensated (and we don't do that yet)
22:10
Bertl
I don't understand the question regarding global shutter limits
22:10
BAndiT1983
is there some fast buffer involved to store the data temporarily?
22:10
Bertl
you mean dedicated two port memory or so?
22:10
BAndiT1983
i was just wondering if global shutter reduces speed or something like that
22:11
BAndiT1983
i don't know how you call it in electronics, for me it's like cache
22:11
Bertl
not really, there is a small amount of in sensor transfer overhead
22:11
Bertl
when the sensel voltages are 'copied' into the back store
22:12
Bertl
there is no dedicated frame buffer memory on the Beta
22:13
Bertl
the Microzed features 1GB of DDR3 SDRAM
22:19
Bertl
this is implemented in two chips from micron
22:19
Bertl
https://www.micron.com/parts/dram/ddr3-sdram/mt41k256m16ha-125
22:20
BAndiT1983
which bit modes are supported for CMV?
22:21
Bertl
they form an x32 bus with typically 533MHz clock IIRC
22:21
Bertl
the current firmware is locked to 12bit
22:22
BAndiT1983
datasheet says 132 fps in that mode
22:23
BAndiT1983
just trying to get an overview what is used and how fast processing goes
22:27
Bertl
that is the limitation from the sensor side at max clock rate and 64bit outputs
22:28
Bertl
with binning you can reach up to 267 and with subsampling up to 528 FPS at full resolution
22:28
BAndiT1983
not bad
22:28
Bertl
at 10bit, you can get 300FPS and 1049 FPS with subsampling
22:29
Bertl
(according to the Cmosis datasheet that is :)
22:30
BAndiT1983
have just reached that part there
22:31
se6astian
off to bed
22:31
se6astian
good night
22:31
se6astian
changed nick to: se6astian|away
22:31
BAndiT1983
night
22:41
BAndiT1983
which settings of CMV the user is/should be allowed to access?
22:42
BAndiT1983
scripts have gain and white balance
22:49
Bertl
allowed should be any of the registers
22:50
Bertl
we do not want to limit access, but typically there will be 'functions' to set specific 'features'
22:50
Bertl
often a 'simple' setting will affect a bunch of registers which need to be set correctly to make it work
22:50
BAndiT1983
sure, was just thinking of encapsulating some calls in general methods, so it's a bit comfortable without searching for all the registers to set gain or similar
22:51
BAndiT1983
currently gain requires gain value of course and ADC range
22:54
BAndiT1983
i suppose that high value of adc range results from setting adc_range_mult bit
22:54
Bertl
I think there are two approaches to this:
22:55
Bertl
the first is to keep the control daemon to a bare minimum and have some kind of 'support' library which handles the dependencies and details (like limits)
22:55
BAndiT1983
can be done by bit fields
22:55
Bertl
the second one is to have some kind of plugins for the control daemon
22:55
Bertl
which do exactly that and provide a generic interface to the outside
22:56
BAndiT1983
there would be a memory adapter, from it i would derive CMV adapter, as it'S mapped
22:56
BAndiT1983
at least it's the plan, to not reinvent the wheel i would "methodize" devmem, as it has almost no methods and all is done in main()
22:57
BAndiT1983
for me it's a little bit of unusual thing, but i'm used to OOP development
22:59
Bertl
devmem is just the file interface to the kernel memory map
22:59
Bertl
once mapped, you can simply access the registers as addresses in your tasks memory
22:59
Alvis
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22:59
BAndiT1983
i know, looked at the source code, wanted to integrate its functionality, to not deploy many processes, at the moment dameon prototype is slim and doesn't require much