Current Server Time: 19:07 (Central Europe)

#apertus IRC Channel Logs

2013/10/14

Timezone: UTC


23:23
Sasha_C
joined the channel
08:19
dmj_nova
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13:12
FergusL
hi there
13:12
Sasha_C
Greetings FergusL. How are you?
13:12
FergusL
Hi Sasha_C, I'm SimonL from the forum
13:13
FergusL
I'm fine ! reading wonderful news daily on the ML
13:13
Sasha_C
nice to hear that :)
13:14
Sasha_C
I'm waiting for Sebastian to come online. I have some questions for him, regarding the creation of new posts on the apertus site
13:42
Bertl
maybe send an e-Mail if it is urgent?
13:42
Sasha_C
it's not urgent, but you're right. I'll send him an email
15:05
Sasha_C
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16:40
se6astian
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16:42
se6astian
good evening, I am back from Linz!
16:43
Bertl
welcome back!
16:47
se6astian
Thanks :)
16:57
se6astian
I friend of mine suggested looking at the parallella FPGA related code, maybe we can (re)use something: https://github.com/parallella
16:57
se6astian
they also use a zynq
16:57
se6astian
maybe the memory controller?
16:58
Bertl
what memory controller?
17:06
se6astian
they must have one :)
17:06
Bertl
well, from the schematic, they are using the PS7 DDR controller (like the zedboard does) just with a 7010 chip
17:07
Bertl
i.e. the zynq-7000 specific, hardened DDR controler present in all zynq chips
17:08
Bertl
so no code, no programmed IP there AFAICT
17:08
se6astian
I see - and that one is not an option for us, or is it the method that would be too slow for us and you tried it already?
17:09
Bertl
that's the one we are using for all memory related stuff
17:09
Bertl
and that very likely will be the one for all future DDR type memory
17:10
Bertl
(unless we see a good reason to build our own memory controller)
17:10
se6astian
I am confused, what are you working on atm? :)
17:10
Bertl
streaming data from the PL via AXI slave ports to the DDR memory
17:11
se6astian
ah, I see
17:11
Bertl
and also streaming data from DDR memory (again via those slave ports) to the PL
17:11
se6astian
I thought the memory controller itself was making trouble
17:14
Bertl
maybe it is, I don't know, we probably have to wait for xilinx to comment on
17:14
Bertl
fact is, that my test code as well as the xilinx example cause data mixup when using more than one channel at the same time
17:15
Bertl
the funny part is that the xilinx example is written in such a way that this mixup/corruption cannot be detected :)
17:16
se6astian
:)
17:16
Bertl
it would make sense to test this on another zedboard, maybe it is just my zynq which is misbehaving
17:16
Bertl
after all, according to xilinx this chip might be quite an early one (with a number of bugs)
17:17
Bertl
(at least that is the explanation so far, why the DNA port doesn't work)
17:18
se6astian
well I can try to help by running it on my zynq tomorrow if you guide me through the process
17:19
Bertl
we can give it a try
17:20
Bertl
but no worries, I'm already thinking about a workaround :)
17:21
se6astian
also good :)
18:03
se6astian
did you write to Thomas btw?
18:03
Bertl
ah, no, it's still on my todo list
18:04
Bertl
feel free to mail him though, basically the script looks fine, and it would be nice to have a script to show the current settings (not just this one)
18:05
Bertl
i.e. interpret as many registers as possible in a human readable and meaningful way
18:15
se6astian
done
19:10
tonsofpcs
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tonsofpcs
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22:02
[1]se6astian
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22:04
se6astian
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22:04
[1]se6astian
changed nick to: se6astian
22:27
se6astian
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22:57
Sasha_C
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