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#apertus IRC Channel Logs

2013/10/14

Timezone: UTC


22:23
Sasha_C
joined the channel
07:19
dmj_nova
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12:12
FergusL
hi there
12:12
Sasha_C
Greetings FergusL. How are you?
12:12
FergusL
Hi Sasha_C, I'm SimonL from the forum
12:13
FergusL
I'm fine ! reading wonderful news daily on the ML
12:13
Sasha_C
nice to hear that :)
12:14
Sasha_C
I'm waiting for Sebastian to come online. I have some questions for him, regarding the creation of new posts on the apertus site
12:42
Bertl
maybe send an e-Mail if it is urgent?
12:42
Sasha_C
it's not urgent, but you're right. I'll send him an email
14:05
Sasha_C
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15:40
se6astian
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15:42
se6astian
good evening, I am back from Linz!
15:43
Bertl
welcome back!
15:47
se6astian
Thanks :)
15:57
se6astian
I friend of mine suggested looking at the parallella FPGA related code, maybe we can (re)use something: https://github.com/parallella
15:57
se6astian
they also use a zynq
15:57
se6astian
maybe the memory controller?
15:58
Bertl
what memory controller?
16:06
se6astian
they must have one :)
16:06
Bertl
well, from the schematic, they are using the PS7 DDR controller (like the zedboard does) just with a 7010 chip
16:07
Bertl
i.e. the zynq-7000 specific, hardened DDR controler present in all zynq chips
16:08
Bertl
so no code, no programmed IP there AFAICT
16:08
se6astian
I see - and that one is not an option for us, or is it the method that would be too slow for us and you tried it already?
16:09
Bertl
that's the one we are using for all memory related stuff
16:09
Bertl
and that very likely will be the one for all future DDR type memory
16:10
Bertl
(unless we see a good reason to build our own memory controller)
16:10
se6astian
I am confused, what are you working on atm? :)
16:10
Bertl
streaming data from the PL via AXI slave ports to the DDR memory
16:11
se6astian
ah, I see
16:11
Bertl
and also streaming data from DDR memory (again via those slave ports) to the PL
16:11
se6astian
I thought the memory controller itself was making trouble
16:14
Bertl
maybe it is, I don't know, we probably have to wait for xilinx to comment on
16:14
Bertl
fact is, that my test code as well as the xilinx example cause data mixup when using more than one channel at the same time
16:15
Bertl
the funny part is that the xilinx example is written in such a way that this mixup/corruption cannot be detected :)
16:16
se6astian
:)
16:16
Bertl
it would make sense to test this on another zedboard, maybe it is just my zynq which is misbehaving
16:16
Bertl
after all, according to xilinx this chip might be quite an early one (with a number of bugs)
16:17
Bertl
(at least that is the explanation so far, why the DNA port doesn't work)
16:18
se6astian
well I can try to help by running it on my zynq tomorrow if you guide me through the process
16:19
Bertl
we can give it a try
16:20
Bertl
but no worries, I'm already thinking about a workaround :)
16:21
se6astian
also good :)
17:03
se6astian
did you write to Thomas btw?
17:03
Bertl
ah, no, it's still on my todo list
17:04
Bertl
feel free to mail him though, basically the script looks fine, and it would be nice to have a script to show the current settings (not just this one)
17:05
Bertl
i.e. interpret as many registers as possible in a human readable and meaningful way
17:15
se6astian
done
18:10
tonsofpcs
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tonsofpcs
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21:02
[1]se6astian
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21:04
se6astian
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21:04
[1]se6astian
changed nick to: se6astian
21:27
se6astian
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21:57
Sasha_C
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