#apertus IRC Channel Logs

mhhh... mh...

nah, never said that, the EU funding is completely independant and targets the AXIOM gamma

when do you think you get the result?

woha... well... i know i guy in vienna, who raised 2,5 millions per year for his assosiation

we where planing "a thing" together some years back in time, but i ve never finished the concept, as it became to large and i wasnt ready for it back than...

or do you need both, to get going?

the AXIOM Beta itself is completely independant from the Gamma of course

well, there will be an AXIOM Gamma sooner or later, but of course, the timeframe and the quality depends on the available resources

yes, but it will take some time of course

(somewhere in the chat logs from yesterday or so)

i am always thinking fundraising money to buy a house on the countryside and get all the developers there, to live cheap and healthy, save a lot of money and time for development :D

sounds good but probably won't work for most developers, as they have families and regular work which actually pays their bills, etc

i always wanted to start out with a cellar in a internetcafe style, but different in the way that you can rent 4-6m² boxes, with a desk and a bench to sleep at, the restroom, showroom, kitchen and livingroom are shared spaces

right now i am experimenting with the work which needs to be done to get most of the food i need over a year from a garden

na, that where dreams in my youth, when that was enough room :D

now that i am getting older, nature becomes more and more important to me

quite the opposite as you can see :D

i am thinking of doing a batterypack prototype

and is the socket connection layout for the modules of the beta done yet?

we have a preliminary connector layout for the shields, but it is not fixed yet

http://vserver.13thfloor.at/Stuff/AXIOM/BETA/io_shield_r.png

what cad program do you use for your layouts and renderings?

for renderings you have to talk with sebastian, I've no idea what was used

well, i guess thats enough information for me now :)

cya

off to bed as well ... have a good one everyone!

you should shoot a test video in there near an accelerator, right?

aombk: we did :)

Hi Bertl, will there be a RTC in the Beta?

yes

it is part of the PIC32

Good Morning! If you are still interested in the 3D LUT module I wrote you can read about it in parts of my bachelors thesis here:

That includes implementation details and results for simulation, fitting, timing and so on. I also included the highest level VHDL Entity so you can see the interface. The rest of the sources and testbenches I can share once I'm done with the thesis.

as you are quite familiar with the topic, I have an interesting question to pose

what I mean is, that what you call LUTbits actually produce the coefficients for a 'normal' matrix color space conversion which is applied to the full pixel information?

I imagine that would produce unacceptable discontinuities at the edges where a new set of coefficients starts.

i.e. is the interpolation smooth over different LUT entries?

Well, with interpolation such as trilinear interpolation yo do get quatiation errors, especially when the pixel is furthest away from the eight nearest LUT support points.

But they are continuous.

but I'm just thinking out loud here, I haven't made any tests or simulations yet

Yeah, I think so but you'd have to include an offset.

I did look into cubic interpolation out of curiousity but that requires 64 LUT data words per lookup which results in a bandwidth of over 1 terabit/second as well as hundreds of hardware multiplicators for that throughput. If you have a large dedicated FPGA for that it's probably doable, but I imagine you want to do other things in the camera as well :D

okay, thanks for the chat, I won't keep you from finishing your thesis, but I hope you are still interested in our project when you're done with it.

Sure, no problem. If you have any further questions, don't hesitate.

have you seen info on Samsung XP941?

PCI-e x4

Anand measured 600MB/sec sequential write on PIC-e 2.0

raw

a single SATA 6G SSD can do 550MB/s

True

and 4096x3072 at 12bit, 30FPS is about 540MByte/s

if you write an open PCIe 2.0 stack on the next weekend, we take care of the required hardware interfaces :)

but just to play a mental game - you're talking about smth in PL not in Linux kernal right?

7015 somehow supports PCIe, XP941 is a PCIe device, being naive I thought it should be fairly straightforward to bring them together

and yes, we are talking FPGA code here, not ARM/kernel

out of interest what kind of "IDE" are you using for your FPGA work?

it is partially hardened but the protocol is done as soft core

anton: we are using vivado on the commandline atm, in combination with a bunch of FOSS tools

thanks for clarify bertl...

you could ask a pilot what to do when reaching stall speeds

Tobe, the 350 euros will be used for developement. Then you'll be able to order the complete camera for 2300 € (at cost). Only people who funded development will be able to order the camera at cost.

hi