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#apertus IRC Channel Logs

2014/09/14

Timezone: UTC


00:14
derWalter
mhhh... mh...
00:16
derWalter
@bertl u always said that the crowdfunding campaign starts when the EU project application is trough, so how did it go then?
00:17
Bertl
nah, never said that, the EU funding is completely independant and targets the AXIOM gamma
00:18
Bertl
and it is currently being processed :)
00:23
derWalter
when do you think you get the result?
00:24
Bertl
with the EU you never know, but we knew that it would take several months, up to a year
00:25
derWalter
woha... well... i know i guy in vienna, who raised 2,5 millions per year for his assosiation
00:26
derWalter
he nearly applied for the head of the wiki foundation, but didnt do it in the end, cause wiki was to screwed up back than (and i guess still is :P)
00:28
derWalter
we where planing "a thing" together some years back in time, but i ve never finished the concept, as it became to large and i wasnt ready for it back than...
00:29
derWalter
say if the eu is opting out but the beta crowd funding suceeds, is there roadmap to get to axiom gamma and vice versa?
00:29
derWalter
or do you need both, to get going?
00:31
Bertl
well, without AXIOM Beta, there will be little development around the AXIOM camera, so the Gamma might still be doable with the EU grant, but naturally at lower quality
00:31
Bertl
the AXIOM Beta itself is completely independant from the Gamma of course
00:50
derWalter
but without eu money no gamma?
00:51
Bertl
well, there will be an AXIOM Gamma sooner or later, but of course, the timeframe and the quality depends on the available resources
00:51
derWalter
okay, so even if the crowdfunding and the eu funding fails, you are still going for the gamma?
00:51
Bertl
yes, but it will take some time of course
00:52
derWalter
i am asking this, cause i read that you said that if the crowdfunding fails you dont know if there will be a gamma
00:52
derWalter
(somewhere in the chat logs from yesterday or so)
00:53
Bertl
it might not be like the Gamma we planned
00:53
derWalter
i am always thinking fundraising money to buy a house on the countryside and get all the developers there, to live cheap and healthy, save a lot of money and time for development :D
00:54
derWalter
i am thinking about that for around 15 years by now...
00:54
Bertl
sounds good but probably won't work for most developers, as they have families and regular work which actually pays their bills, etc
00:55
Bertl
(where developers here refer to open source and free software developers)
00:55
derWalter
i always wanted to start out with a cellar in a internetcafe style, but different in the way that you can rent 4-6m² boxes, with a desk and a bench to sleep at, the restroom, showroom, kitchen and livingroom are shared spaces
00:56
derWalter
well, the bills would be cut down quite a bit, by moving into a shared house on the countryside
00:56
derWalter
right now i am experimenting with the work which needs to be done to get most of the food i need over a year from a garden
00:57
Bertl
yeah, but do you want to leave your family and friends and live in 4-6m² boxes?
00:57
derWalter
na, that where dreams in my youth, when that was enough room :D
00:57
derWalter
when the virtual world was basically my whole live
00:58
derWalter
now that i am getting older, nature becomes more and more important to me
00:58
derWalter
and community
00:58
derWalter
quite the opposite as you can see :D
00:59
derWalter
btw
00:59
derWalter
i am thinking of doing a batterypack prototype
01:00
derWalter
do you know where to go to build one, or in other words, do you have good connections to the tu-workshops, metalab and/or angewandte?
01:01
derWalter
and is the socket connection layout for the modules of the beta done yet?
01:09
Bertl
no special connections in this regard, but you can certainly contact the metalab folks or the team members from 'angewandte'
01:09
Bertl
we have a preliminary connector layout for the shields, but it is not fixed yet
01:10
Bertl
http://vserver.13thfloor.at/Stuff/AXIOM/BETA/io_shield_l.png
01:10
Bertl
http://vserver.13thfloor.at/Stuff/AXIOM/BETA/io_shield_r.png
01:11
derWalter
how to identify the people from the angewandte?
01:12
derWalter
what cad program do you use for your layouts and renderings?
01:15
Bertl
currently we are using Eagle but we plan to switch to KiCad
01:15
Bertl
for renderings you have to talk with sebastian, I've no idea what was used
01:22
derWalter
okay :)
01:24
derWalter
well, i guess thats enough information for me now :)
01:24
derWalter
as i ve to get up as early as seven? ... i ll go to bed now ^^ cya in a few days bb
01:24
Bertl
cya
01:28
derWalter
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01:39
Bertl
off to bed as well ... have a good one everyone!
01:39
Bertl
changed nick to: Bertl_zZ
02:25
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04:33
Morethink
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Morethink
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05:42
aombk
oh cern ohl i see
05:43
aombk
you should shoot a test video in there near an accelerator, right?
07:13
Meinereiner
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08:24
Bertl_zZ
changed nick to: Bertl
08:24
Bertl
morning folks!
08:24
Bertl
aombk: we did :)
08:25
Bertl
but it was desy (EHSM) not cern
08:32
dakorl
Hi Bertl, will there be a RTC in the Beta?
08:39
sb0_
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08:42
Bertl
yes
09:07
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09:26
dakorl
I didn't find a RTC on the picozed, so which chip will you use? It would be good for timelapse to rtcwake the system to save power...
09:39
Bertl
it is part of the PIC32
09:40
Bertl
http://ww1.microchip.com/downloads/en/DeviceDoc/60001191C.pdf
12:10
Meinereiner
Good Morning! If you are still interested in the 3D LUT module I wrote you can read about it in parts of my bachelors thesis here:
12:10
Meinereiner
https://www.filesplat.com/?p=d&id=A88MJzMzz2tsCYAu
12:13
Meinereiner
That includes implementation details and results for simulation, fitting, timing and so on. I also included the highest level VHDL Entity so you can see the interface. The rest of the sources and testbenches I can share once I'm done with the thesis.
12:23
Bertl
excellent! I'll work my way through it. thanks!
12:26
Bertl
as you are quite familiar with the topic, I have an interesting question to pose
12:28
Bertl
wouldn't it be possible to combine 3D LUTs with matrix operations in such a way that you basically define the matrix coefficients via an initial LUT?
12:29
Bertl
what I mean is, that what you call LUTbits actually produce the coefficients for a 'normal' matrix color space conversion which is applied to the full pixel information?
12:40
Meinereiner
I'm still actually fairly new to the subject so I can't speak from authority. I imagine one problem with that setup would be the interpolation, since you would have to do at least 9 interpolations per lookup for all 3x3 matrix coefficients instead of three right?
12:45
dakorl
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12:45
Bertl
I'm more thinking of dropping the interpolation part and instead getting the coefficients from the lookup table directly and then simply applying them to the input data
12:52
Meinereiner
I imagine that would produce unacceptable discontinuities at the edges where a new set of coefficients starts.
12:52
Bertl
how does the interpolation approach avoid that atm?
12:53
Bertl
i.e. is the interpolation smooth over different LUT entries?
12:55
Bertl
trilinear suggests otherwise :)
12:55
Meinereiner
Well, with interpolation such as trilinear interpolation yo do get quatiation errors, especially when the pixel is furthest away from the eight nearest LUT support points.
12:57
Meinereiner
And the boundaries are not smooth, you'd need a higher order interpolator for that., which has a drastic increase in resource usage.
12:58
Meinereiner
But they are continuous.
13:00
Bertl
yes, they are continuous, but not smooth, and you could probably make sure that the matrix coefficients also create a contiuous result, no?
13:01
Bertl
but I'm just thinking out loud here, I haven't made any tests or simulations yet
13:02
Bertl
and certainly the traditional 3D-LUT has a bunch of advantages starting with ease of use
13:02
Meinereiner
Yeah, I think so but you'd have to include an offset.
13:06
Bertl
yes, sorry, the offset is required atm as well
13:08
Meinereiner
I did look into cubic interpolation out of curiousity but that requires 64 LUT data words per lookup which results in a bandwidth of over 1 terabit/second as well as hundreds of hardware multiplicators for that throughput. If you have a large dedicated FPGA for that it's probably doable, but I imagine you want to do other things in the camera as well :D
13:10
Bertl
right :)
13:11
Bertl
okay, thanks for the chat, I won't keep you from finishing your thesis, but I hope you are still interested in our project when you're done with it.
13:12
Bertl
for the adaptation to the xilinx environment, I do not see a real problem from what I've seen in the pdf
13:12
Meinereiner
Sure, no problem. If you have any further questions, don't hesitate.
13:13
Bertl
great! thanks!
13:17
anton
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13:18
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13:52
anton
Hi, Bertl
13:52
anton
have you seen info on Samsung XP941?
13:52
anton
it's 22 * 80mm
13:52
anton
PCI-e x4
13:52
anton
512Gb version is 349 GBP now
13:52
anton
Anand measured 600MB/sec sequential write on PIC-e 2.0
13:53
anton
30fps ras is about 480MB/sec if I'm not mistaken
13:53
anton
raw
13:53
Bertl
yeah, but 600MB/s is a waste of PCIe 2.0 x4 :)
13:53
Bertl
a single SATA 6G SSD can do 550MB/s
13:54
Bertl
and that means we could in theory handle 4 of them
13:55
anton
True
13:55
anton
I guess I was thinking of a "quick and dirty" internal storage for the initial release of the Beta
13:55
Bertl
and 4096x3072 at 12bit, 30FPS is about 540MByte/s
13:55
Bertl
there is nothing quick and dirty with PCIe 2.0
13:56
Bertl
if you write an open PCIe 2.0 stack on the next weekend, we take care of the required hardware interfaces :)
13:58
anton
fat chance with 0 experience :)
13:59
anton
but just to play a mental game - you're talking about smth in PL not in Linux kernal right?
14:00
anton
XP941 is taking AHCI commands over PCIe somehow
14:08
anton
7015 somehow supports PCIe, XP941 is a PCIe device, being naive I thought it should be fairly straightforward to bring them together
14:10
Bertl
trust me, it isn't
14:10
Bertl
and yes, we are talking FPGA code here, not ARM/kernel
14:12
Bertl
but we might be able to utilize an open core or extend one
14:17
anton
out of interest what kind of "IDE" are you using for your FPGA work?
14:27
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15:33
tyrone_
Bertl: i have read the irc log and i have seen the talk about pci express. the zynq hasn't got a integrated pcie core? is it done as a soft implementation?
15:36
Bertl
it is partially hardened but the protocol is done as soft core
15:38
jucar
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15:38
Bertl
anton: we are using vivado on the commandline atm, in combination with a bunch of FOSS tools
15:39
tyrone_
ufff it's a logiccore ip :-( i didn't know that.....
15:39
tyrone_
thanks for clarify bertl...
15:41
Bertl
no problem.
15:59
aombk
you could ask a pilot what to do when reaching stall speeds
16:27
FergusL
hahaha
16:39
Tobe
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16:41
Tobe
Hi I just have a little question, the 350 price is for the camera without the sensor and shipped. Or do I have to pay the extra 2300 when the camera is shipped (with the sensor)? Thanks for your response.
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17:12
philippej
Tobe, the 350 euros will be used for developement. Then you'll be able to order the complete camera for 2300 ⬠(at cost). Only people who funded development will be able to order the camera at cost.
17:18
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19:15
aombk
actually, the thumbnail/screenshot of the youtube campaign video is tux/open source over a danger sign. just noticed it. maybe thats not the best thumbnail, i dont know
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19:40
vic_
hi
19:40
aombk
hi
20:51
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