Current Server Time: 04:17 (Central Europe)

#apertus IRC Channel Logs

2015/07/14

Timezone: UTC


00:07
fsteinel
left the channel
00:07
fsteinel_
joined the channel
04:59
LordVan
joined the channel
06:04
Bertl_oO
off to bed now ... have a good one everyone!
06:04
Bertl_oO
changed nick to: Bertl_zZ
06:24
g3gg0
joined the channel
06:38
se6astian|away
changed nick to: se6astian
07:42
g3gg0
left the channel
08:05
fsteinel_
changed nick to: fsteinel
08:43
jucar
joined the channel
10:01
Bertl_zZ
changed nick to: Bertl
10:01
Bertl
morning folks!
10:18
jucar
left the channel
12:41
LordVan
hi
12:41
Bertl
hey
13:23
LordVan
you did the PCB and FPGA stuff right?
13:24
Bertl
probably, depends on what "the PCB" and "the FPGA stuff" is :)
13:24
alesage
joined the channel
13:24
alesage
left the channel
13:24
alesage
joined the channel
13:32
LordVan
well
13:32
LordVan
axiom ^^
13:32
LordVan
Manfred told me about it on the way back from the meeting yesterday
13:33
Bertl
I see :)
13:36
Michele_
joined the channel
13:40
Bertl
hey Michele_!
13:40
LordVan
looks good :D - the PCB ^^
13:40
Bertl
thanks!
13:40
LordVan
only looked it of course ;)
13:40
LordVan
I did some PCB stuff back in school (HTL) ;)
13:42
se6astian
hello!
13:42
Bertl
LordVan: what kind of design?
13:43
LordVan
well the basic stuff you do in school and mill out then ;)
13:43
LordVan
not really any mult-layer stuff
13:43
Bertl
yeah, but any specific project?
13:43
LordVan
ah that
13:43
LordVan
well let me think
13:44
LordVan
it is quite a long time ago ^^
13:45
LordVan
i honestly do not remember what it did anymore ^^ some small projects (PCB had to be < EuroCard format) and be millable .. some analogue stuff but a few simple micro controller (Atmel 8051) things
13:45
LordVan
nothing particularily complicated
13:45
LordVan
one time it was I2C bus with 80512
13:45
LordVan
8051
13:45
LordVan
to access a temperature sensor
13:46
LordVan
but that never got actually made on pcb due to the school year being over ;)
13:46
Bertl
ah, yes, very popular
13:47
LordVan
yeah simple to program
13:47
LordVan
i was the only one in class who used linux to develop instead of the "standard" MS Dos tools haha
13:47
LordVan
that was fun ..
13:47
LordVan
getting the toolcahin to work
13:50
LordVan
i sort of want to do that kind of work again
13:50
LordVan
it was quite interesting
13:50
LordVan
but i forgot so much
13:58
mars_
with a modern microcontroller, I guess ;)
13:59
LordVan
gtg. cu
14:00
LordVan
left the channel
14:00
mars_
or not... ^^
14:53
se6astian
Team Talk Vol 5 is out!
14:53
se6astian
https://apertus.org/axiom-team-talk-volume5-article-july-2015
15:01
se6astian
now time to leave the axiom office :)
15:03
mars_
you mean the 2000sqm office in the first district? ;)
15:05
se6astian
changed nick to: se6astian|away
15:34
jucar
joined the channel
15:49
jucar
left the channel
15:55
mike
joined the channel
15:55
mike
changed nick to: Guest78647
15:57
Guest78647
would anyone be able to answer a few questions about the image acquisition pipeline?
15:58
Bertl
probably
15:59
Guest78647
thanks!
16:00
Guest78647
https://www.apertus.org/sites/default/files/20140910012757-BETA_interface.jpg
16:01
Guest78647
so, the FPGA performs pixel reordering etc., then it travels over some interconnect to the ARM core onto DRAM?
16:02
Bertl
the zynq combines the FPGA fabric (PL) with two hardened cores (PS) and a dram memory controller
16:02
Guest78647
I should prefix this with my intentions - I'm working on a university research project for a modular sensor interface that works with the Video 4 Linux subsystem - the Axiom seems like a really handy reference :)
16:03
Bertl
the data is moved from the FPGA fabric to the DRAM via the hardened dram controller
16:03
Bertl
so the arm cores are not involved in this part
16:03
Guest78647
ah ok
16:05
Guest78647
and the image stored in memory is in CV12000 RAW format at this stage? DNG conversion is done on the ARM cores?
16:05
Bertl
it usually is, but you could modify it in the FPGA before writing it out to memory
16:06
Guest78647
of course
16:07
Guest78647
so out of interest, in the Beta you have image overlays etc.
16:07
Guest78647
is the ARM chip powerful enough to process this 4K framebuffer?
16:08
Bertl
again, the arm cores are not really involved in the overlays
16:08
Bertl
or more precisely, the arm cores "create" overlays and "control" what is done with them
16:08
Guest78647
oh? so overlays are all done on the FPGA
16:08
Bertl
but the actual image processing happens in the FL fabric
16:08
Guest78647
ah I see, so the FPGA is doing the actual compositing
16:08
Bertl
*PL
16:08
Guest78647
got it
16:11
Guest78647
so essentially the ARM cores are just used for control
16:11
Guest78647
all the heavy-lifting is done on the FPGA?
16:11
Bertl
yup
16:12
Guest78647
interesting
16:13
Guest78647
thank you very much for your help - I wish you the best of luck with the project!
16:13
Bertl
you're welcome! and thanks!
16:14
Guest78647
left the channel
16:21
Michele_
left the channel
16:36
Bertl
off for now ... bbl
16:36
Bertl
changed nick to: Bertl_oO
16:50
slikdigit
joined the channel
16:55
jlf
joined the channel
17:30
se6astian|away
changed nick to: se6astian
18:24
baldand_
joined the channel
18:30
Bertl_oO
left the channel
18:30
morrigan
left the channel
18:30
baldand
left the channel
18:30
mithro
left the channel
18:39
morrigan1
joined the channel
18:40
Bertl_oO
joined the channel
18:41
g3gg0
joined the channel
18:49
jlf
left the channel
19:30
jucar
joined the channel
19:34
se6astian
changed nick to: se6astian|away
19:52
mithro
joined the channel
20:33
alesage
left the channel
20:33
alesage
joined the channel
20:33
alesage
left the channel
20:33
alesage
joined the channel
21:39
jucar
left the channel
21:57
jucar
joined the channel
22:21
intracube
changed nick to: intracube|away