#apertus IRC Channel Logs

off to bed now ... have a good one everyone!

Yes

yes

please, not everbody at once! :)

okay so in my experience, the 'simple' task of getting a simple serial link to work and measuring error rate is not trivial

felix_, _florent__ maybe?

even when the clock and data have the right phase relation at the source, you'll get some additional delay for the clock through the clock distribution networks on the reveiver side and you'll need to compensate that

a note here: do not fool yourself and think that you can get away with static delays in a high speed setup, even if the clocks are synchronized and the data has a known phase relation to the clock

at a certain data rate (probably anything above 200MHz) the jitter and clock variation is enough to mess up any static delays and ultimately increase the BER dramatically

having clocks with the same nominal frequency, but form different sources have to be treated as asynchronous or you're in for some really hard to debug trouble

but yeah, the clocking and adjusting the phases of the signals is what you'll likely spend most time on

1) the clock is generated by the source, the data is phase aligned, both clock and data are transmitted to the destination

3) both ends have a free running clock of 'about the same' frequency, data is aligned to the source clock, but sampled with the destination clock

the big advantage of 1) and 2) is that the amount of data per unit of time will always be the same on both ends

i.e. have stuffing bits/bytes you can drop or add when required

now a fourth way to handle things is to regenerate the clock from the data received

one way to actively synchronize a PLL to some data packets is by constant dynamic phase shifting based on the received data

aSobhy, apurvanandan[m]: any questions so far?

without dedicated hardware support it usually is

Oh, I didn't knew this.

not yet

?

e.g. manchester coding, 10 for '1' and 01 for '0'

now given that there is no hardware support for clock recovery, how do you approach sampling here?

Sorry I dont know about clock recovery in so much depths :(

basically you need to have a local clock and sample at a higher frequency to figure out where the transitions happen

once you know that, you can adjust your local clock (either frequency or phase) to match the transitions

which means that you have to handle all the ugly stuff of two free running clocks

now let's take a look at the second aspect of high speed serial, the verification

in short, how to estimate the BER

?

Use a PRNG

with psudo random number generator

this is rather straight forward and you can get arbitrarily long random sequences with very simple designs (only a few gates)

the tricky part in testing is to synchronize both sides so that they send and expect the same sequence

the simplest approach here is to have a 'magic sequence' to reset the LFSRs

specifically the two basic designs (fibonaccy and galois) typically leave out all zero or all one states

so you can use this specific data word to reset the receiver

Will we need some feedback that module has been reset

Ok

Yes

Ok got it

yep

so you need to prepare for a clock domain crossing there to avoid problems

note that most codes define so called 'comma symbols'

yep, that's what i meant

okay, any input, comments, questions, etc?

yeah I don't understand what the caveat rule means ?

aSobhy: let's say the serial clock runs at 500MHz and the data is transferred on each clock cycle (SDR)

so you end up with one byte at 50MHz clock

you design then does BER accounting at this clock rate (two counters, total/fail)

let's say you report the current total/fail counters via SERIAL

typically you will retrieve the data via JTAG or output it over UART or some other way

okay, thanks felix_!

oh and if you have questions, you can always ping me here; might take some time that i'll respond though

- encodings, why and how?

- dynamic delay adjustments (sender and/or receiver)

bonus points if you can explain the stuff next time and/or find new and useful information online :)

Yes, most probably

hmm, did we change the time for next monday?

an hour later

okay, so for me, 17:00 UTC is fine as well

OK thanks Bertl :)

and for apurvanandan[m] ?

^_^

we will be busy over the weekend, but I'll try to answer those questions in a timely manner

ah you told that we run in the case 3

how can we separate it tp be two clocks ?

in the current design, the zynq has two clocks and a number of PLLs which can derive frequencies from that

Bertl can you share how you use openocd with your jtag

apurvanandan[m]: I'm currently using a digilent HS2 or HS3 jtag adapter (USB) with openocd

but uploading a configuration to the MachXO2 is not very complicated, so it doesn't depend on special jtag programmers

we will go through programming the MachXO2 in the Beta when we are back from the Maker Faire

http://openocd.org/doc/html/Debug-Adapter-Hardware.html

Ok, will try for xup and tell you if face any problem

try with something simple first, e.g. discovery

then use openocd with different configurations to get jtag chain discovery working

apurvanandan[m]: what is opencd ?

Its for debugging HW?

ok I find it

Hello BAndiT1983|away ,

Let me continue where i left off...

Also looked for MVP model

I would be great if u could explain the how modules will interact

hi Dev_, i would expect to hear from you how it should interact, as it's a part of gsoc

okay, I will try to understand it

what about the approach which i explained for playButton , Can u please provide feedback on that

Yes, to visualize playing video: Each time we click the playbutton , it will pause or play the video. The slider will update its positon when the button is clicked.

So whenever we have to keep track of change in state of playbutton, and update the slider value using ui->horizantal-slider->setValue();

but you still require some modules who will consume the events and also to play the video

and when the frame is loaded, an event should be executed to notify other modules about it, also one which will update the slider position

The*

the event/signal could provide the variable which state was toggled, e.g. through enum PlaybackState::PAUSED

It looks typical now :( , don't have idea how it should be implemented

to get started you can also start by googling "video player architecture"

example -> https://i.stack.imgur.com/SPe5g.png

As rought idea , clicking of play button will start loading of frame and pausing it will stop loading of frames ,

In-between updating slider will take place

updating slider happens not in the playback slider, it only provides a method to do it from other modules

example sequence: playback button is clicked, event is fired on the event hub, frame provider is subscribed to it and starts to load next frames and send an event to the event hub, which video output consumes, frame provider also fires an event that frame is loaded (maybe same event is sufficient), then playback slider is updated by certain module

the task is not simple at first, know it from OC development, as i've started to work on the project to improve my software dev skills for my job

Yes , I will also try to learn asap

if i haven'T mentioned some useful pages -> sourcemaking.com

Yes , I will try to understand it more

no problem

so next high speed serial link talk is next monday at 17:00 CEST, right?

i.e. 19:00 CEST

great!

good night

off to bed now ... have a good one everyone!