#apertus IRC Channel Logs

hi ,

<vhdl-task1>

double check that you use proper indentation and code formatting ...

and for the simulation is a do file is acceptable or a test bench ?

modelSim

okay

off to bed now ... have a good one everyone!

what SerDes ratio do we intend to keep in task 1 of T871 VHDL

apurvanandan[m]: in task 1 you want to allow for 8, 10 and 12 bit on the parallel output

Hi

Iam using now quartus prime lite edition for knowing the max speed

the tools used there are Vivado (for Xilinx) and Diamond (for Lattice), both in the 'Free' (as beer) version provided from the FPGA manufacturer

I have test my code on quartus on fpga altera maxV and optmized it but i achived 100Mhz as a maximum speed i had reached

I didn't use a hardened ddr or serdes i wite it my self. Can you advice me what i should do

well, I just checked with the MaxV DC/Switching specs, abd about 300MHz I/O should be doable there

but I can take a look at the code if you have something to show

Ok iwill send my git-link

Quartus is the tool, Intel (former Altera) the manufacturer, MaxV the CPLD family

what I'm mostly interested in is the VHDL :)

aSobhy_: you might also want to get a proper IRC client instead of the web client

yeah, the lines have been blurred over the years ...

+3

"+3" is a wrong type sorry for that

well, you want to clean up the code a little bit to make it more readable, stuff like:

currently it looks more like a severe case of VHDL diarrhea ...

if I'm reading the code correctly, you 'assume' that the bitstream is packetized and contains a length marker 'at the beginning'

iam really sorry serial2parallel.vhd should be removed i forgot to remove it

now it is and Iam formatting the code

the transmition ends when the process ends

but I'm fine with your scenario as well if you can speed it up :)

so their would be a header of every message i receive which has the bit slip to be adjusted the next frame ?

nope, the typical setup is that the serial data has a 'known' bit depth and the data needs to be synchronized via bitslip (e.g. to training codes)

which can provide data in 8, 10 and 12bit depth

when the ADC is idle, it send a control word, let's say "BAF" which is truncated to 10/8 bit on the lower bit depths

and adjust the bitslip to match the expected training pattern

off for now

let's say the clock for the ADC is 100MHz and it send the data at 600MHz so it can send 50M samples at 12bit, 60M samples at 10bit and 75M samples at 8bit resolution

btw, I added this example to the challenge task for clarification

Sorry for delay i was on my way to home

excuse me is there a diffrence between bitslip and bit depth

https://forums.xilinx.com/t5/Spartan-Family-FPGAs/understanding-BITSLIP-one-more-time/td-p/105327

Which of the 4 types of SerDes we have to implement?

i dont think he meant these 4: logic, wired or, ioserdes and gt* :)

but i thought that the bitslip and the bit depth are the same and i will change it