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#apertus IRC Channel Logs

2019/03/14

Timezone: UTC


23:08
RexOrCine
changed nick to: RexOrCine|away
00:24
aSobhy
hi ,
00:24
aSobhy
how i can submit my code and what are the requirements ?
00:24
aSobhy
<vhdl-task1>
00:29
aSobhy
the deliverable list **
00:42
Umori
left the channel
00:42
Bertl
best to upload it somewhere (e.g. github) and preferably add some instructions how to build
00:43
Bertl
double check that you use proper indentation and code formatting ...
00:48
Bertl
then simply paste the url, either here or in private, whatever you prefer
00:56
aSobhy
and for the simulation is a do file is acceptable or a test bench ?
00:58
Bertl
both is fine, what tools do you use?
00:59
aSobhy
modelSim
00:59
Umori
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01:01
Bertl
okay
02:34
Y_G
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03:35
Bertl
off to bed now ... have a good one everyone!
03:35
Bertl
changed nick to: Bertl_zZ
04:39
BAndiT1983|away
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04:50
Y_G
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05:05
BAndiT1983
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05:32
intrac
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06:19
apurvanandan[m]
what SerDes ratio do we intend to keep in task 1 of T871 VHDL
06:42
se6astian|away
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08:32
shivamgoyal
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08:36
se6astian
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shivamgoyal
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shivamgoyal
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08:55
shivamgoyal
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09:50
se6astian|away
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09:54
danieeel
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danieeeel
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danieel
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danieeel
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10:11
shivamgoyal
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10:20
shivamgoyal
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11:10
danieeeel
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11:29
shivamgoyal
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11:52
intrac
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11:56
shivamgoyal
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12:56
Bertl_zZ
changed nick to: Bertl
12:57
Bertl
morning folks!
12:58
Bertl
apurvanandan[m]: in task 1 you want to allow for 8, 10 and 12 bit on the parallel output
13:03
se6astian
good day!
13:13
RexOrCine|away
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13:24
shivamgoyal
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13:28
shivamgoyal
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shivamgoyal
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13:35
BAndiT1983|away
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14:45
aSobhy_
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14:51
aSobhy_
Hi
14:52
aSobhy_
I want to know what is the targeted fpga that i will simulate on it ?
14:57
aSobhy_
Iam using now quartus prime lite edition for knowing the max speed
14:58
aSobhy_
<VHDL chalnge task1>
15:01
BAndiT1983
changed nick to: BAndiT1983|away
15:06
Bertl
well, depending on the final task you are interested in, you are going to work with Xilinx 7Series FPGA (ZYNQ or Artix) or Lattice MachXO2
15:07
Bertl
the tools used there are Vivado (for Xilinx) and Diamond (for Lattice), both in the 'Free' (as beer) version provided from the FPGA manufacturer
15:08
Bertl
but for the challenge itself you can use other tools as well as long as the result can be verified by us
15:14
aSobhy_
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15:31
aSobhy_
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15:33
aSobhy_
I have test my code on quartus on fpga altera maxV and optmized it but i achived 100Mhz as a maximum speed i had reached
15:34
Bertl
100MHz for the serial link or the parallel data?
15:35
aSobhy_
I didn't use a hardened ddr or serdes i wite it my self. Can you advice me what i should do
15:35
aSobhy_
Serial
15:37
Bertl
well, I just checked with the MaxV DC/Switching specs, abd about 300MHz I/O should be doable there
15:38
Bertl
it is not a specifically fast FPGA to work with but 100MHz serial speed sounds a little low
15:38
Bertl
but I can take a look at the code if you have something to show
15:43
Bertl
actually the MaxV is sold as CPLD :)
15:47
aSobhy_
Ok iwill send my git-link
15:48
aSobhy_
But it is on quartus as fpga ?!
15:49
Bertl
Quartus is the tool, Intel (former Altera) the manufacturer, MaxV the CPLD family
15:49
BAndiT1983|away
changed nick to: BAndiT1983
15:49
Bertl
what I'm mostly interested in is the VHDL :)
15:59
aSobhy_
left the channel
15:59
Bertl
aSobhy_: you might also want to get a proper IRC client instead of the web client
16:00
Kjetil
Max10 is sold as a FPGA
16:01
Bertl
yeah, the lines have been blurred over the years ...
16:06
aSobhy
i have send the git link to that mail *email address removed*
16:07
aSobhy
+3
16:10
aSobhy
i actually use both but i will talk from the web client from now :)
16:11
aSobhy
"+3" is a wrong type sorry for that
16:12
Bertl
serial2parallel.vhd is a leftover?
16:13
Bertl
well, you want to clean up the code a little bit to make it more readable, stuff like:
16:14
Bertl
remove excessive empty lines, add spaces around operands, fix indentation to be consistent, etc
16:15
Bertl
currently it looks more like a severe case of VHDL diarrhea ...
16:22
Bertl
but looking at the code, I'm not really surprised you do not achieve more than 100MHz ...
16:24
Bertl
if I'm reading the code correctly, you 'assume' that the bitstream is packetized and contains a length marker 'at the beginning'
16:33
shivamgoyal
left the channel
16:34
aSobhy
iam really sorry serial2parallel.vhd should be removed i forgot to remove it
16:35
aSobhy
and also ser2par.vhd was not its latest version
16:35
aSobhy
now it is and Iam formatting the code
16:49
aSobhy
no iam not assuming that the bitstream from the beginning produce every (8/10/12) bit from serial a corresponding parallel bits
16:49
aSobhy
the transmition ends when the process ends
16:51
Bertl
well, a more realistic scenario is that the serial input bitdepth can be selected somehow (e.g. via control lines) and is constant during transmission
16:55
Bertl
but I'm fine with your scenario as well if you can speed it up :)
16:55
Bertl
anyway, let me know when you've cleaned up the code
16:56
aSobhy
so their would be a header of every message i receive which has the bit slip to be adjusted the next frame ?
16:56
aSobhy
okay thanks for your help :D
16:57
Bertl
nope, the typical setup is that the serial data has a 'known' bit depth and the data needs to be synchronized via bitslip (e.g. to training codes)
16:57
Bertl
so, let's assume the FPGA is connected to an ADC
16:57
Bertl
which can provide data in 8, 10 and 12bit depth
16:58
Bertl
two control lines select the 'mode' for the ADC and in some way the mode for the deserializer as well
16:59
Bertl
when the ADC is idle, it send a control word, let's say "BAF" which is truncated to 10/8 bit on the lower bit depths
17:00
Bertl
link training (which is not part of task 1) would now look at the 12/10/8 bit words
17:00
Bertl
and adjust the bitslip to match the expected training pattern
17:01
Bertl
once that is done, the ADC is activated and the real data comes in 8/10/12 bit packets which get deserialized by your code
17:01
se6astian
off for now
17:01
se6astian
changed nick to: se6astian|away
17:02
Bertl
let's say the clock for the ADC is 100MHz and it send the data at 600MHz so it can send 50M samples at 12bit, 60M samples at 10bit and 75M samples at 8bit resolution
17:02
Bertl
*sends
17:21
Bertl
btw, I added this example to the challenge task for clarification
17:23
BAndiT1983
changed nick to: BAndiT1983|away
17:59
aSobhy
Sorry for delay i was on my way to home
18:03
aSobhy
its a hand-shacking protocol at first right ?
18:05
aSobhy
excuse me is there a diffrence between bitslip and bit depth
18:06
aSobhy
?
18:21
se6astian|away
changed nick to: se6astian
18:26
Bertl
no handshaking
18:26
Bertl
https://forums.xilinx.com/t5/Spartan-Family-FPGAs/understanding-BITSLIP-one-more-time/td-p/105327
18:42
aSobhy
ok thanks :)
18:42
BAndiT1983|away
changed nick to: BAndiT1983
18:46
Bertl
you're welcome!
19:02
illwieckz
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19:03
illwieckz
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19:13
apurvanandan[m]
Which of the 4 types of SerDes we have to implement?
19:19
Bertl
apurvanandan[m]: 4 types?
19:56
danieel
i dont think he meant these 4: logic, wired or, ioserdes and gt* :)
20:23
BAndiT1983
changed nick to: BAndiT1983|away
20:23
BAndiT1983|away
changed nick to: BAndiT1983
21:00
aSobhy
i have formatted the code :)
21:13
aSobhy
but i thought that the bitslip and the bit depth are the same and i will change it
21:16
BAndiT1983
changed nick to: BAndiT1983|away
21:30
se6astian
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22:00
RexOrCine
changed nick to: RexOrCine|away
22:16
futarisIRCcloud
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