| 23:00 | Bertl_oO | off to bed now ... have a good one everyone!
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| 04:18 | Bertl | morning folks!
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| 07:44 | Bertl | back now ..
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| 08:16 | se6astian | good day!
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| 09:11 | sagnikbasu | Hi
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| 09:20 | Bertl | hey, how's going?
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| 09:25 | sagnikbasu | Hi Bertl , so I posted some queries in the lab page of GSOC project "Real time sobel filter in fpga".Could you please check them?
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| 09:30 | niculescu_vlad | joined the channel |
| 09:31 | Bertl | well, the flow chart is not entirely correct
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| 09:33 | sagnikbasu | Ok..is it the connection between the camera sensor and fpga ?
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| 09:33 | Bertl | first, the camera sensor is connected to the FPGA, so the data is first there
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| 09:35 | sagnikbasu | so how many signals do i expect from the sensor ?
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| 09:35 | Bertl | then the data is stored into DDR memory and the HDMI output pipeline fetches this data again from memory for the output
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| 09:35 | niculescu_vlad | left the channel |
| 09:35 | Bertl | now, depending on the actual use case, the filter will be either active on the sensor data
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| 09:36 | Bertl | i.e. in the input/sensor pipeline
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| 09:36 | Bertl | or on the output pipeline
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| 09:37 | Bertl | access to multiple frames is not available at the moment (for various reasons)
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| 09:38 | Bertl | the sensor itself is connected with a bunch of LVDS pairs
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| 09:38 | Bertl | (up to 80 max) which are used to transfer the data
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| 09:38 | Bertl | clock rate between 200 and 600 MHz
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| 09:39 | Bertl | also, it is a CMOS sensor (not a CCD)
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| 09:40 | sagnikbasu | So I assume that we will be getting pixel data from 80 such pairs simultaneously..
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| 09:40 | sagnikbasu | i.e. 80 LVDS pairs
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| 09:41 | sagnikbasu | and apply the pipelined convolutiom kernel to them..
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| 09:41 | sagnikbasu | sorry *convolution
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| 09:58 | Bertl | yes, data is retrieved in parallel (current setup has 32 channels, and the sensor transfers blocks of two rows)
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| 10:18 | sagnikbasu | Bertl : Thanks . I will change my design accordingly.
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| 11:12 | niculescu_vlad | hello
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| 11:13 | niculescu_vlad | did you manage to implement something else?
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| 11:13 | niculescu_vlad | one question: where should we post files?
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| 11:13 | niculescu_vlad | with attempts
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| 11:20 | Elbehery | hey <niculescu_vlad>
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| 11:21 | Elbehery | so far i submitted the files on my github repo, and added a link at the ideas page comment section
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| 11:21 | Elbehery | i think this is ok
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| 11:22 | niculescu_vlad | ok. I will do the same on my google drive
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| 11:24 | Elbehery | cool, but in case you have some time, posting this on github with a readme file + license should probably be the best thing
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| 11:25 | niculescu_vlad | ok
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| 11:26 | Elbehery | btw have you checked the current posted prototypes ?
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| 11:31 | niculescu_vlad | no. I've seen the modules you wrote. I think the PWM can be written as a state machine to be easier to understand. I can try it. And I will also try to implement a PID algorithm in verilog
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| 11:31 | niculescu_vlad | did you try the I2C module?
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| 11:32 | niculescu_vlad | I suggest to write all your codes as state machines. It is easier to follow the information flow
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| 11:32 | Elbehery | they already are FSMs
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| 11:32 | Elbehery | check the state diagram at the readme file
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| 11:34 | niculescu_vlad | i didn;t see any case
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| 11:35 | Elbehery | ohh, let me send you the repo. link
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| 11:36 | Elbehery | https://github.com/ELBe7ery/i2c_draft_gsoc/tree/master/TOP
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| 11:36 | Elbehery | i2cslave + pwm + top module + tb
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| 11:37 | niculescu_vlad | yes I saw
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| 11:38 | niculescu_vlad | if the I2C works this is good
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| 11:38 | niculescu_vlad | but I suggested to write the PWG gen within a single always block
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| 11:38 | niculescu_vlad | to avoid problems
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| 11:39 | Elbehery | pwm generator ?
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| 11:40 | Elbehery | hmm, good point this is probably should be tested on a real FPGA though then other iterative design path to enhance the rtl
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| 11:41 | niculescu_vlad | yes. Usually generating the bitfile can produce problems when using always@(*)
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| 11:41 | niculescu_vlad | like combinational loops
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| 11:42 | mithro | of anyone has time, could they proof read https://hdmi2usb.tv/gsoc/fpga/hardware/python/linux/2017/03/15/gsoc-announcement/ ?
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| 11:43 | mithro | s/of/if/
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| 11:49 | Elbehery | perfect! i am sharing this
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| 12:06 | ArrunM | hello everyone. Can't figure out where to put proposal for Gsoc?
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| 12:11 | niculescu_vlad | I rewrote it
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| 12:11 | niculescu_vlad | in a single always
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| 12:13 | niculescu_vlad | Here
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| 12:13 | niculescu_vlad | https://drive.google.com/open?id=0B4vrlXPPuUghVU5qaHFwR2NWYjA
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| 12:13 | niculescu_vlad | it is a 10 bit pwm
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| 12:14 | niculescu_vlad | now if the i2c works fine, I want to write the PID controler
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| 12:14 | niculescu_vlad | controller*
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| 12:15 | usmankhan | Hey ArrunM, Google will provide official link to submit the proposal after 20th March. However, you can write the draft proposal and share it on either github or google doc
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| 12:16 | ArrunM | thnaks!! usmankhan
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| 12:20 | niculescu_vlad | Bertl, we should discuss about the number of sensors. This is actually the number of inputs in my control algorithm and I want to start designing it.
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| 12:25 | Bertl | niculescu_vlad: there are temp sensors in the image sensor, inside the zynq and on the power board
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| 12:26 | Bertl | optionally there is an additional temp sensor on the sensor board but that's not used at the moment
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| 12:53 | ArrunM_ | Hello bertl, can you tell me the exact pins used for communication between zync and mach2
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| 12:53 | ArrunM_ | needed for manual place and route
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| 13:05 | Bertl | ArrunM_: please check the schematic of the mainboard for the pin details
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| 13:09 | ArrunM_ | sorry to bother you but I really dont know the tag name to search
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| 13:11 | Bertl | will take some time, rather busy at the moment
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| 13:11 | ArrunM_ | no problem!!
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| 15:20 | Elbehery | hey <niculescu_vlad>
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| 15:20 | niculescu_vlad | Hi
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| 15:21 | niculescu_vlad | Sorry for being idle. Classes...
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| 15:21 | Elbehery | just had my internet back, checked your comment
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| 15:21 | Elbehery | ohh no problem
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| 15:21 | Elbehery | by the way
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| 15:21 | Elbehery | " I wrote a simplified but functional iteration of PWM generator and now, I want to start working at the PIC controller."
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| 15:21 | Elbehery | as much as i understand
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| 15:22 | Elbehery | the software will be running on the Zynq FPGA which has an ARM processor not a PIC
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| 15:22 | niculescu_vlad | Sorry. I wanted to write PID
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| 15:22 | niculescu_vlad | Not PIC
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| 15:23 | Elbehery | ohh great then
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| 15:23 | niculescu_vlad | I will edit my comment. Thank you
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| 15:24 | Elbehery | and also have some question related to the pwm gen
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| 15:25 | Elbehery | i am confused, how can we interface this generator with the I2c slave. Cant find the 8/16 bit input register that sets the output duty cycle
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| 15:26 | niculescu_vlad | done
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| 15:28 | Elbehery | great, just checked this
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| 15:28 | niculescu_vlad | Thank you for your observation
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| 15:28 | Elbehery | no problem :) hey did you see my last msg or this was sent after you got dc ?
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| 15:29 | niculescu_vlad | which message?
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| 15:29 | Elbehery | okay letme sent this again
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| 15:29 | Elbehery | i was asking about the pwm generator posted on the comment
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| 15:29 | Elbehery | so far cant figure out how to set the duty cycle of this generator
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| 15:30 | niculescu_vlad | by modifying the TH parameter
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| 15:30 | niculescu_vlad | which is the threshold
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| 15:30 | niculescu_vlad | it is on 10 bits. So the duty cycle is TH/1024
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| 15:31 | Elbehery | ohh missed reading this input so sorry :)
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| 15:31 | niculescu_vlad | it's ok
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| 15:40 | niculescu_vlad | if admitted in SOC, I guess we will work in Vivado
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| 15:40 | niculescu_vlad | isn't it?
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| 15:42 | Elbehery | i don't know honestly
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| 15:43 | niculescu_vlad | Bertl?
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| 19:48 | Elbehery | A quick question, can we say this high level block diagram is valid for the t732 ?
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| 19:48 | Elbehery | https://raw.githubusercontent.com/ELBe7ery/i2c_draft_gsoc/master/Top%20module/Screenshots/BLOCK_DIAGRAM_enhanced.png
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| 22:05 | Bertl_oO | Elbehery: yep, looks good
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| 22:06 | Bertl_oO | niculescu_vlad: Vivado for Zynq, Lattice Diamond for MachXO2 at the moment
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| 22:12 | Bertl_oO | off to bed now ...
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| 22:12 | Bertl_oO | changed nick to: Bertl_zZ
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