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#apertus IRC Channel Logs

2017/03/14

Timezone: UTC


00:00
Bertl_oO
off to bed now ... have a good one everyone!
00:00
Bertl_oO
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05:18
Bertl_zZ
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05:18
Bertl
morning folks!
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se6astian|away
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se6astian
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07:05
Bertl
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se6astian|away
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se6astian
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08:44
Bertl_oO
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08:44
Bertl
back now ..
09:12
se6astian|away
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09:16
se6astian
good day!
10:10
sagnikbasu
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10:11
sagnikbasu
Hi
10:20
Bertl
hey, how's going?
10:21
niculescu_vlad
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10:25
sagnikbasu
Hi Bertl , so I posted some queries in the lab page of GSOC project "Real time sobel filter in fpga".Could you please check them?
10:30
niculescu_vlad
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10:31
Bertl
well, the flow chart is not entirely correct
10:33
sagnikbasu
Ok..is it the connection between the camera sensor and fpga ?
10:33
Bertl
first, the camera sensor is connected to the FPGA, so the data is first there
10:35
sagnikbasu
so how many signals do i expect from the sensor ?
10:35
Bertl
then the data is stored into DDR memory and the HDMI output pipeline fetches this data again from memory for the output
10:35
niculescu_vlad
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10:35
Bertl
now, depending on the actual use case, the filter will be either active on the sensor data
10:36
Bertl
i.e. in the input/sensor pipeline
10:36
niculescu_vlad
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10:36
Bertl
or on the output pipeline
10:37
Bertl
access to multiple frames is not available at the moment (for various reasons)
10:38
Bertl
the sensor itself is connected with a bunch of LVDS pairs
10:38
Bertl
(up to 80 max) which are used to transfer the data
10:38
Bertl
clock rate between 200 and 600 MHz
10:39
Bertl
also, it is a CMOS sensor (not a CCD)
10:40
sagnikbasu
So I assume that we will be getting pixel data from 80 such pairs simultaneously..
10:40
sagnikbasu
i.e. 80 LVDS pairs
10:40
niculescu_vlad
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10:41
sagnikbasu
and apply the pipelined convolutiom kernel to them..
10:41
sagnikbasu
sorry *convolution
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Elbehery
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10:58
Bertl
yes, data is retrieved in parallel (current setup has 32 channels, and the sensor transfers blocks of two rows)
11:18
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11:18
sagnikbasu
Bertl : Thanks . I will change my design accordingly.
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arpu
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Elbehery
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tyrone
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Vlad__
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Vlad__
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12:12
Elbehery
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12:12
niculescu_vlad
hello
12:13
niculescu_vlad
did you manage to implement something else?
12:13
niculescu_vlad
one question: where should we post files?
12:13
niculescu_vlad
with attempts
12:20
Elbehery
hey <niculescu_vlad>
12:21
Elbehery
so far i submitted the files on my github repo, and added a link at the ideas page comment section
12:21
Elbehery
i think this is ok
12:22
niculescu_vlad
ok. I will do the same on my google drive
12:23
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12:24
Elbehery
cool, but in case you have some time, posting this on github with a readme file + license should probably be the best thing
12:25
niculescu_vlad
ok
12:26
Elbehery
btw have you checked the current posted prototypes ?
12:31
niculescu_vlad
no. I've seen the modules you wrote. I think the PWM can be written as a state machine to be easier to understand. I can try it. And I will also try to implement a PID algorithm in verilog
12:31
niculescu_vlad
did you try the I2C module?
12:32
niculescu_vlad
I suggest to write all your codes as state machines. It is easier to follow the information flow
12:32
Elbehery
they already are FSMs
12:32
Elbehery
check the state diagram at the readme file
12:34
niculescu_vlad
i didn;t see any case
12:35
Elbehery
ohh, let me send you the repo. link
12:36
Elbehery
https://github.com/ELBe7ery/i2c_draft_gsoc/tree/master/TOP
12:36
Elbehery
i2cslave + pwm + top module + tb
12:37
niculescu_vlad
yes I saw
12:37
usmankhan
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12:38
niculescu_vlad
if the I2C works this is good
12:38
niculescu_vlad
but I suggested to write the PWG gen within a single always block
12:38
niculescu_vlad
to avoid problems
12:39
Elbehery
pwm generator ?
12:40
Elbehery
hmm, good point this is probably should be tested on a real FPGA though then other iterative design path to enhance the rtl
12:41
niculescu_vlad
yes. Usually generating the bitfile can produce problems when using always@(*)
12:41
niculescu_vlad
like combinational loops
12:42
mithro
of anyone has time, could they proof read https://hdmi2usb.tv/gsoc/fpga/hardware/python/linux/2017/03/15/gsoc-announcement/ ?
12:43
mithro
s/of/if/
12:49
Elbehery
perfect! i am sharing this
13:05
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13:06
ArrunM
hello everyone. Can't figure out where to put proposal for Gsoc?
13:08
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usmankhan
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13:11
niculescu_vlad
I rewrote it
13:11
niculescu_vlad
in a single always
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usmankhan
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13:13
niculescu_vlad
Here
13:13
niculescu_vlad
https://drive.google.com/open?id=0B4vrlXPPuUghVU5qaHFwR2NWYjA
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Elbehery
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13:13
niculescu_vlad
it is a 10 bit pwm
13:14
niculescu_vlad
now if the i2c works fine, I want to write the PID controler
13:14
niculescu_vlad
controller*
13:15
usmankhan
Hey ArrunM, Google will provide official link to submit the proposal after 20th March. However, you can write the draft proposal and share it on either github or google doc
13:16
ArrunM
thnaks!! usmankhan
13:20
niculescu_vlad
Bertl, we should discuss about the number of sensors. This is actually the number of inputs in my control algorithm and I want to start designing it.
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AndroUser2
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13:25
Bertl
niculescu_vlad: there are temp sensors in the image sensor, inside the zynq and on the power board
13:26
Bertl
optionally there is an additional temp sensor on the sensor board but that's not used at the moment
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13:53
ArrunM_
Hello bertl, can you tell me the exact pins used for communication between zync and mach2
13:53
ArrunM_
needed for manual place and route
14:00
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14:05
Bertl
ArrunM_: please check the schematic of the mainboard for the pin details
14:09
ArrunM_
sorry to bother you but I really dont know the tag name to search
14:11
Bertl
will take some time, rather busy at the moment
14:11
ArrunM_
no problem!!
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BAndiT1983|away
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BAndiT1983
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16:20
Elbehery
hey <niculescu_vlad>
16:20
niculescu_vlad
Hi
16:21
niculescu_vlad
Sorry for being idle. Classes...
16:21
Elbehery
just had my internet back, checked your comment
16:21
Elbehery
ohh no problem
16:21
Elbehery
by the way
16:21
Elbehery
" I wrote a simplified but functional iteration of PWM generator and now, I want to start working at the PIC controller."
16:21
Elbehery
as much as i understand
16:22
Elbehery
the software will be running on the Zynq FPGA which has an ARM processor not a PIC
16:22
niculescu_vlad
Sorry. I wanted to write PID
16:22
niculescu_vlad
Not PIC
16:23
Elbehery
ohh great then
16:23
niculescu_vlad
I will edit my comment. Thank you
16:24
Elbehery
and also have some question related to the pwm gen
16:25
Elbehery
i am confused, how can we interface this generator with the I2c slave. Cant find the 8/16 bit input register that sets the output duty cycle
16:25
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16:26
niculescu_vlad
done
16:28
Elbehery
great, just checked this
16:28
niculescu_vlad
Thank you for your observation
16:28
Elbehery
no problem :) hey did you see my last msg or this was sent after you got dc ?
16:29
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16:29
niculescu_vlad
which message?
16:29
Elbehery
okay letme sent this again
16:29
Elbehery
i was asking about the pwm generator posted on the comment
16:29
Elbehery
so far cant figure out how to set the duty cycle of this generator
16:30
niculescu_vlad
by modifying the TH parameter
16:30
niculescu_vlad
which is the threshold
16:30
niculescu_vlad
it is on 10 bits. So the duty cycle is TH/1024
16:31
Elbehery
ohh missed reading this input so sorry :)
16:31
niculescu_vlad
it's ok
16:40
niculescu_vlad
if admitted in SOC, I guess we will work in Vivado
16:40
niculescu_vlad
isn't it?
16:42
Elbehery
i don't know honestly
16:43
niculescu_vlad
Bertl?
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Bertl
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20:48
Elbehery
A quick question, can we say this high level block diagram is valid for the t732 ?
20:48
Elbehery
https://raw.githubusercontent.com/ELBe7ery/i2c_draft_gsoc/master/Top%20module/Screenshots/BLOCK_DIAGRAM_enhanced.png
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BAndiT1983
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23:05
Bertl_oO
Elbehery: yep, looks good
23:06
Bertl_oO
niculescu_vlad: Vivado for Zynq, Lattice Diamond for MachXO2 at the moment
23:12
Bertl_oO
off to bed now ...
23:12
Bertl_oO
changed nick to: Bertl_zZ