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#apertus IRC Channel Logs

2019/10/13

Timezone: UTC


00:49
vup
Bertl: are there any tricks to debugging hdmi?
01:06
BAndiT1983
changed nick to: BAndiT1983|away
01:44
vup
is there anything that needs to be done to enable the level shifter on the plugin modules?
08:34
BAndiT1983|away
changed nick to: BAndiT1983
08:58
niemand
joined the channel
10:30
Bertl_zZ
changed nick to: Bertl
10:30
Bertl
morning folks!
10:30
Bertl
vup: what level shifter?
10:34
niemand
left the channel
10:39
anuejn
Bertl: the PTN3363 on the hdmi plugin modules
10:40
anuejn
we were trying to test the hdmi on the micro but somehow we werent able to measure the clock or data signal past that chip
10:40
anuejn
(with custom code / not yours)
10:40
anuejn
before, there was signal present
10:40
Bertl
ah, yeah, that's tricky without the sink
10:41
anuejn
we tried to short hpd to 5v in the cable
10:41
Bertl
first there is #OE, which needs to be pulled low
10:42
Bertl
then HPD (sink side) which needs to be 5V
10:42
Bertl
and I think DDET needs to be low as well
10:42
Bertl
(not 100% sure about that though)
10:43
Bertl
it also requires an active clock
10:44
anuejn
the hdmi clock?
10:44
Bertl
yup
10:44
anuejn
is there a lower frequency bound to that clock?
10:45
Bertl
probably but it can be quite slow IIRC
10:45
anuejn
k
10:45
Bertl
i.e. if there is no activity on any input, the part seems to power down
10:46
anuejn
hm...
10:46
anuejn
that shouldnt have been the problem
10:46
Bertl
I'm not sure about checks on the output, but as it is CML it wouldn't hurt to have a 50R termination on it as well
10:47
anuejn
how did you debug the module?
10:47
Bertl
I used an HDMI passthrough with taps
10:47
anuejn
do you have an hdmi splitter?
10:47
anuejn
ah nice, i see
10:48
anuejn
maybe we have to build something similiar
10:49
Bertl
I did design a break-out for HDMI, which might be simple enough to extend to a passthrough with SMA
10:51
anuejn
hm... maybe we will also try with the beta hardware first
10:51
anuejn
thanks :)
10:51
Bertl
just took a look at the breakout, and yes, simply mirroring the connector would work for a pass through
10:52
Bertl
so if you need something like that, I can easily adjust it, you just have to order and populate it
12:07
Bertl
anuejn, vup: just let me know :)
12:07
BAndiT1983
changed nick to: BAndiT1983|away
12:13
anuejn
tx
12:13
anuejn
we will see
12:14
anuejn
but i think we will go with the hdmi-splitter solution before, because we have that
12:14
Bertl
okay
12:32
BAndiT1983|away
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13:36
comradekingu
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14:01
apurvanandan[m]
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14:10
apurvanandan[m]
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14:27
BAndiT1983
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14:48
Spirit532
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14:48
Spirit532
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16:20
comradekingu
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16:44
Bertl
off for now ... bbl
16:44
Bertl
changed nick to: Bertl_oO
18:23
BAndiT1983|away
changed nick to: BAndiT1983
18:32
jhlink
The dev board has arrived!!
18:33
se6ast1an
great
19:45
jhlink
Right? I'm excited.
19:45
jhlink
Anyone have any tips or words of warning?
19:46
jhlink
Something like C's "Don't free non-allocated variables or die" but for FPGA's?
20:25
LordVan
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20:46
se6ast1an
off to bed, good night
20:57
BAndiT1983
changed nick to: BAndiT1983|away
21:44
vup
jhlink: i would say try avoiding the xilinx / vivado block diagram stuff
21:45
vup
And if you are looking for verilog / vhdl alternatives: i like nmigen alot
21:47
jhlink
I just really want to learn the basics that isn't bad advice ( e.g. always type cast the return of malloc ), and then start contributing. :)
21:57
LordVan
left the channel
22:36
danieel
jhlink: what? you cant compare rtl to sequential code
22:51
jhlink
Right. I think that was a poor analogy. The idea was establishing a solid foundation with the right information.
22:53
jhlink
When learning something new, I don't know what I don't know. In the context of C, for the sake of example, I'd follow whatever is given to me because I don't know any better.
22:53
jhlink
I'd really like to avoid situations of learning bad habits in rtl.
22:53
jhlink
:)
23:47
intracube
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23:59
intracube
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