| 01:49 | vup | Bertl: are there any tricks to debugging hdmi?
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| 02:06 | BAndiT1983 | changed nick to: BAndiT1983|away
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| 02:44 | vup | is there anything that needs to be done to enable the level shifter on the plugin modules?
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| 09:34 | BAndiT1983|away | changed nick to: BAndiT1983
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| 11:30 | Bertl_zZ | changed nick to: Bertl
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| 11:30 | Bertl | morning folks!
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| 11:30 | Bertl | vup: what level shifter?
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| 11:39 | anuejn | Bertl: the PTN3363 on the hdmi plugin modules
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| 11:40 | anuejn | we were trying to test the hdmi on the micro but somehow we werent able to measure the clock or data signal past that chip
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| 11:40 | anuejn | (with custom code / not yours)
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| 11:40 | anuejn | before, there was signal present
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| 11:40 | Bertl | ah, yeah, that's tricky without the sink
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| 11:41 | anuejn | we tried to short hpd to 5v in the cable
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| 11:41 | Bertl | first there is #OE, which needs to be pulled low
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| 11:42 | Bertl | then HPD (sink side) which needs to be 5V
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| 11:42 | Bertl | and I think DDET needs to be low as well
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| 11:42 | Bertl | (not 100% sure about that though)
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| 11:43 | Bertl | it also requires an active clock
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| 11:44 | anuejn | the hdmi clock?
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| 11:44 | Bertl | yup
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| 11:44 | anuejn | is there a lower frequency bound to that clock?
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| 11:45 | Bertl | probably but it can be quite slow IIRC
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| 11:45 | anuejn | k
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| 11:45 | Bertl | i.e. if there is no activity on any input, the part seems to power down
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| 11:46 | anuejn | hm...
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| 11:46 | anuejn | that shouldnt have been the problem
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| 11:46 | Bertl | I'm not sure about checks on the output, but as it is CML it wouldn't hurt to have a 50R termination on it as well
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| 11:47 | anuejn | how did you debug the module?
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| 11:47 | Bertl | I used an HDMI passthrough with taps
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| 11:47 | anuejn | do you have an hdmi splitter?
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| 11:47 | anuejn | ah nice, i see
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| 11:48 | anuejn | maybe we have to build something similiar
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| 11:49 | Bertl | I did design a break-out for HDMI, which might be simple enough to extend to a passthrough with SMA
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| 11:51 | anuejn | hm... maybe we will also try with the beta hardware first
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| 11:51 | anuejn | thanks :)
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| 11:51 | Bertl | just took a look at the breakout, and yes, simply mirroring the connector would work for a pass through
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| 11:52 | Bertl | so if you need something like that, I can easily adjust it, you just have to order and populate it
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| 13:07 | Bertl | anuejn, vup: just let me know :)
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| 13:07 | BAndiT1983 | changed nick to: BAndiT1983|away
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| 13:13 | anuejn | tx
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| 13:13 | anuejn | we will see
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| 13:14 | anuejn | but i think we will go with the hdmi-splitter solution before, because we have that
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| 13:14 | Bertl | okay
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| 17:44 | Bertl | off for now ... bbl
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| 17:44 | Bertl | changed nick to: Bertl_oO
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| 19:32 | jhlink | The dev board has arrived!!
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| 19:33 | se6ast1an | great
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| 20:45 | jhlink | Right? I'm excited.
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| 20:45 | jhlink | Anyone have any tips or words of warning?
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| 20:46 | jhlink | Something like C's "Don't free non-allocated variables or die" but for FPGA's?
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| 21:46 | se6ast1an | off to bed, good night
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| 21:57 | BAndiT1983 | changed nick to: BAndiT1983|away
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| 22:44 | vup | jhlink: i would say try avoiding the xilinx / vivado block diagram stuff
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| 22:45 | vup | And if you are looking for verilog / vhdl alternatives: i like nmigen alot
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| 22:47 | jhlink | I just really want to learn the basics that isn't bad advice ( e.g. always type cast the return of malloc ), and then start contributing. :)
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| 23:36 | danieel | jhlink: what? you cant compare rtl to sequential code
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| 23:51 | jhlink | Right. I think that was a poor analogy. The idea was establishing a solid foundation with the right information.
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| 23:53 | jhlink | When learning something new, I don't know what I don't know. In the context of C, for the sake of example, I'd follow whatever is given to me because I don't know any better.
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| 23:53 | jhlink | I'd really like to avoid situations of learning bad habits in rtl.
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| 23:53 | jhlink | :)
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