#apertus IRC Channel Logs

morning folks!

apurvanandan[m]: nobody asked about the speed grade :)

btw we landed https://github.com/apertus-open-source-cinema/axiom-beta-firmware/pull/100 yesterday, so no more binary blobs needed for the firmware ;)

_florent__: does litepcie support PCIe Gen2 on -1 speedgrade artix 7's?

Gen 2 is 5 GT/s IIRC, so you need high speed MGTs

(from DS180) GTP transceivers in CP, CS, FT, and FG packages support data rates up to 6.25 Gb/s.

speed grade -2 and -3 go up to 6.6Gb/s in the listed packages

xilinx is really good at scattering information over several hundreds of pages long pdf's

yes, they do excellent work there :)

yes, but if you aren't paying 100% attention things like

from 600 Mb/s to max. rates of 6.6 Gb/s up to 28.05 Gb/s, offering a

easily catch you off guard

so the question then is, how much can you go over spec on -1 speed grade ;)

big meeting starting in ~30 minutes

Bertl: what were the pass_* files used for again?

they are partially used is prep_spkfan.sh

they are pass through designs for the MachXO2 (RFE)

wait it's the other way around

so pass_spkfan* and prep_spkfan can be removed?

at the moment we only use pass_spi, as both the speaker and the fan are not properly handled yet in the FPGA

for 'normal operation' none of those are required

i am also interesting in anything required for bringup

ok

the all caps makes it much easier to find in logs :)

for those participating for the first time let me briefly explain

this is organized by one person holding the meeting (currently me - but it might also be done by someone else occasionally)

and say "yes I want to report about my task"

we try to keep this brief and quick

we can do a bit of Q&A after each person but not a lengthy discussion please

this is when people who are busy or want to get back to their tasks can decide if they want to stay and discuss or leave and work

eg: http://irc.apertus.org/index.php?day=13&month=05&year=2019#87

http://irc.apertus.org/index.php lists the chat log of every day

one line per topic discussed

right, so much for the introduction

send me a pm

apurvanandan[m] already said in pms that he is in the country side currently and internet connectivity might not be the best

Actually this week was mainly spent by me for 1. reading the links Bertl gave in previous meeting. 2.Sufficient time was spent( wasted )on getting softwares ready ie Vivado.

well, for the communit bonding phase I'd say it's fine :)

absolutely!

thanks for the report, Bertl please go ahead then as speaker #2

besides the usual business (reworking and testing Betas)

(plugins, breakouts, remote prototypes, etc)

Oh that really awesome :D

and we had a number of discussions about FPGA communications

also successfully managed to recover from Maker Faire Vienna and prepare for Maker Faire Berlin :)

thanks!

I didn't work a lot their was a little things I have done. Since the last week was my projects discussion

I had viewed the schematic design of the 2 MachXO2 and understand them

currently understanding the LVDS pll at the SoC main

I am Currently working on Playback which includes extending of playbacksliders present in OC codebase with its events. In this respect, I was trying to update the slider position each time when we press the playButton using horizontal-slider->setValue(); using a simple loop from zero to max (horizontal-slider->maximum()) and keep updating (increasing) it until we again click the playbutton.

That's it se6astian

I haven't provided him this approach yet

great, then you can discuss it already right after this meeting

okay, se6astian thanks

I did test several approaches on the fpga, these approaches will be used to test the core, I found that the best one was to used AXI DMA and write software bare metal to use it.

after the core is finished, I will test it with this approach.

I have explored several approaches as well to expand the core to include clip header, frame header and frame tail to be able to generate valid clip.

i.e. use the existing Arch Linux, fetch data from DDR and write it back to DDR

bare metal seemed simpler, but I would like to read more about how to use it in Arch Linux, if you have links to help me in that regard it would be great.

in any case, we should discuss this later

Ok, this would be all for now.

Nira originally asked me to share her progress because she is still in class right now

Nira: please go ahead

I also checked what you have on the GitHub and did a little scheme for helping me understand how did you distribute everything.

I think that's all

thanks Nira, great

if anyone else wants to share progress, pm me now please, in the meantime I will also cover some points

next maker faire next weekend will be even bigger though

and from the apertus° community there will also be quite a big meeting

in Berlin

other exciting news are that the AXIOM project and its hardware will be showcased in the museum of contemporary art design laboratory for a long term exhibition

are we already that vintage? ;)

BAndiT1983: more visitors you mean?

according to the list, we are around 7 people

same order of magnitude!

was attending night of museums in frankfurt on saturday, really hard to tell what is new art and which is old

cnc milled enclosure metal parts have been ordered for the AXIOM Beta compact enclosure and should be shipped soon

new flyers will arrive tomorrow just in time for bringing them to berlin: https://lab.apertus.org/M11#1427

we will see how much we can pay rex to add dry british humor jokes to the "script"

se6astian, nah, no need to, as he is already fascinated by Max and the beard

thats it from my side

nice, will try to visit it next time in vienna

so if there are no more reports, let's figure out a date and time for the next meeting

monday is fine here, later is fine as well

aSobhy, you can send it to any mentor, in case se6astian is not available too

you can, best CC you primary mentor as well yes

just because the exams will start the next week I'll be eager to attend but It will depend on the next exam

sure it won't be a habit :D

yes

I am about to pack the stuff for Maker faire berlin into my car and drive off

so I will attend only for a few minutes

Dev_, have seen it, as i was already here and also checking logs regularly

okay BAndiT1983

Dev_, have you evaluated how this would be used by the application? as the events should only notify about clicked buttons or moved slider in the playback control

also don't forget about MVP, as the slider should be updated from other modules

yup

is there a solution to test it with Arch Linux with my board? maybe using micro design?

check with vup or anuejn for detail and if you have any problems

Fares: you should be able to use the latest axiom-micro image from https://github.com/apertus-open-source-cinema/axiom-beta-firmware/releases

for the DDR memory access, it would be great to use the high speed readers/writers we have on the Beta firmware, but of course you can use the Xilinx DMA for testing as well

i would advise against the xilinx axi dma core, as it is much harder to work with than the axihp_{reader,writer}'s of the beta, and you need to use the vivado's strange block diagrams

no the beta readers/writers work a bit different

the most important difference being, that you need to provide the address yourself

you need to convert it using https://github.com/apertus-open-source-cinema/axiom-beta-firmware/blob/master/makefiles/in_chroot/to_raw_bitstream.py

and echo "name_of_.bit" > /sys/class/fpga_manager/fpga0/firmware

as far as I know (from the problems on the forums :)

> the beta readers/writers work *a bit* different

in one the data is provided on a fixed address, and DMA is set up from userspace

in the other the address is configured via AXI registers and the FPGA side bursts data into the given address range

so in the latter the core it self is responsible to control the DMA not from the userspace correct?

the readers and writers have a FIFO attached and basically from this point on you can treat them as stream interface

you can simply reuse the existing address generators and their AXI interface for userspace control

they make some assumptions yes

the one written in migen on github?

yes

yes that is the one

thank you Bertl and vup

let us know if there are any problems ...

yeah, that's how the 'channels' in AMBA/AXI are designed

yeah, It doesn't seem simple :)

off for now ... bbl