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#apertus IRC Channel Logs

2019/05/13

Timezone: UTC


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Bertl_zZ
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08:21
Bertl
morning folks!
08:21
se6astian
good day
08:21
Bertl
apurvanandan[m]: nobody asked about the speed grade :)
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se6astian
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se6astian|away
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11:48
vup2
btw we landed https://github.com/apertus-open-source-cinema/axiom-beta-firmware/pull/100 yesterday, so no more binary blobs needed for the firmware ;)
11:49
Bertl
\o/
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vup2
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12:02
se6astian
great!
12:04
Nira
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felix___
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BAndiT1983|away
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15:14
supragya_
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15:17
vup
_florent__: does litepcie support PCIe Gen2 on -1 speedgrade artix 7's?
15:18
vup
xilinx says you need speedgrade -2 for Gen2 on artix 7...
15:20
Bertl
Gen 2 is 5 GT/s IIRC, so you need high speed MGTs
15:23
supragya_
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15:24
Bertl
(from DS180) GTP transceivers in CP, CS, FT, and FG packages support data rates up to 6.25 Gb/s.
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Nira|away
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15:26
Bertl
speed grade 1 only features up to 3.75Gb/s (see ds181)
15:26
Bertl
speed grade -2 and -3 go up to 6.6Gb/s in the listed packages
15:27
vup
ah right
15:28
vup
xilinx is really good at scattering information over several hundreds of pages long pdf's
15:28
vup
s/several/several,/
15:30
Bertl
yes, they do excellent work there :)
15:31
Bertl
but to be fair, it is in the places where it belongs (overview and ac/dc characteristics)
15:35
vup
yes, but if you aren't paying 100% attention things like
15:35
vup
High-speed serial connectivity with built-in multi-gigabit transceivers
15:35
vup
from 600 Mb/s to max. rates of 6.6 Gb/s up to 28.05 Gb/s, offering a
15:35
vup
special low-power mode, optimized for chip-to-chip interfaces.
15:35
vup
easily catch you off guard
15:36
Bertl
marketing speak ... usually can be ignored :)
15:37
vup
so the question then is, how much can you go over spec on -1 speed grade ;)
15:41
supragya_
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16:29
se6astian
big meeting starting in ~30 minutes
16:40
niemand
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niemand
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16:42
vup
Bertl: what were the pass_* files used for again?
16:42
vup
pass_min.cfg pass_spi.cfg pass_spi.svf pass_spi.ufm pass_spkfan.cfg pass_spkfan.svf pass_spkfan.ufm pass.svf.flash
16:43
vup
they are partially used is prep_spkfan.sh
16:43
vup
which i also don't know whether it is still used or not
16:48
Bertl
they are pass through designs for the MachXO2 (RFE)
16:49
vup
ok, but pass_min and pass_spi are only used in prep_spkfan.sh which you said some time ago shouldn't be relevant anymore
16:49
vup
wait it's the other way around
16:50
vup
only pass_spkfan is used by prep_spkfan and the others are not used by any script atleast
16:50
vup
so pass_spkfan* and prep_spkfan can be removed?
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Fares
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16:52
Bertl
at the moment we only use pass_spi, as both the speaker and the fan are not properly handled yet in the FPGA
16:52
Bertl
for testing speaker and fan the pass_spkfan ist required
16:53
Bertl
for 'normal operation' none of those are required
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Dev_
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16:58
vup
i am also interesting in anything required for bringup
16:59
Bertl
well, then you probably want to keep them all
16:59
vup
ok
17:00
se6astian
MEETING TIME!
17:00
BAndiT1983
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BAndiT1983|away
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17:00
se6astian
the all caps makes it much easier to find in logs :)
17:00
se6astian
so welcome to the reinstatement of our weekly team/gsoc meetings here on irc
17:01
se6astian
for those participating for the first time let me briefly explain
17:01
se6astian
in the first part of the meeting we will try to keep discussion to a minimum and rather give everyone an uninterrupted chance to share what he/she has been working on in the recent week
17:02
se6astian
this is organized by one person holding the meeting (currently me - but it might also be done by someone else occasionally)
17:02
se6astian
this person (me) asks everyone present to PM me (private message me), thats when you double click on a persons name in most IRC clients
17:03
se6astian
and say "yes I want to report about my task"
17:03
se6astian
then I will put all speakers into order (most of the time in the order that I receive requests) and ask each person to report and will hand the word to the next speaker once that person is done
17:04
se6astian
we try to keep this brief and quick
17:04
se6astian
so a few minutes per person reporting is the goal
17:04
BAndiT1983
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BAndiT1983|away
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17:04
se6astian
we can do a bit of Q&A after each person but not a lengthy discussion please
17:05
se6astian
once all people reported and nobody is left we can start discussing certain matters in more detail
17:05
se6astian
this is when people who are busy or want to get back to their tasks can decide if they want to stay and discuss or leave and work
17:06
se6astian
meetings are publically logged so you can read up on past meetings anytime
17:06
se6astian
eg: http://irc.apertus.org/index.php?day=13&month=05&year=2019#87
17:06
se6astian
is today
17:06
se6astian
http://irc.apertus.org/index.php lists the chat log of every day
17:06
se6astian
for some time we also did meeting minutes on the wiki: https://wiki.apertus.org/index.php/IRC_Meeting_Notes
17:06
se6astian
one line per topic discussed
17:07
se6astian
but its extra work so depending on who has time/wants to do this we might not do it all the time
17:07
se6astian
right, so much for the introduction
17:08
se6astian
who is here and wants to report for the first time!?!
17:08
se6astian
send me a pm
17:08
se6astian
and we start off with apurvanandan[m], please go ahead
17:10
se6astian
apurvanandan[m] already said in pms that he is in the country side currently and internet connectivity might not be the best
17:11
se6astian
so interruptions are expected
17:12
apurvanandan[m]
Actually this week was mainly spent by me for 1. reading the links Bertl gave in previous meeting. 2.Sufficient time was spent( wasted )on getting softwares ready ie Vivado.
17:13
apurvanandan[m]
This is not much I know.
17:13
Bertl
well, for the communit bonding phase I'd say it's fine :)
17:14
Bertl
*community
17:14
se6astian
absolutely!
17:14
apurvanandan[m]
I will definitely spend time more efficiently from this week.
17:15
se6astian
thanks for the report, Bertl please go ahead then as speaker #2
17:15
Bertl
okay
17:15
Bertl
besides the usual business (reworking and testing Betas)
17:15
Bertl
I managed to assemble most of the hardware required for GSoC 2019
17:16
Bertl
(plugins, breakouts, remote prototypes, etc)
17:16
Bertl
I also designed a simple LDO based power supply
17:16
apurvanandan[m]
Oh that really awesome :D
17:16
Bertl
to allow our students to power those without special lab equippment
17:17
Bertl
and we had a number of discussions about FPGA communications
17:17
Bertl
as well as hardware in general both FPGA and remote related
17:18
Bertl
also successfully managed to recover from Maker Faire Vienna and prepare for Maker Faire Berlin :)
17:18
Bertl
that's it from my side for this week
17:18
se6astian
thanks!
17:19
se6astian
aSobhy: your turn
17:19
aSobhy
I didn't work a lot their was a little things I have done. Since the last week was my projects discussion
17:19
aSobhy
what I have done:
17:20
aSobhy
I had viewed the schematic design of the 2 MachXO2 and understand them
17:21
aSobhy
Read about SPI protocol that I never used it before
17:23
aSobhy
currently understanding the LVDS pll at the SoC main
17:23
aSobhy
thats all
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se6astian
thanks aSobhy!
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Fares
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17:24
se6astian
Dev_: you are next
17:24
Fares
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17:24
Dev_
Hello , With Reference to Task T763 (Frameserver for OC)
17:24
Dev_
I am Currently working on Playback which includes extending of playbacksliders present in OC codebase with its events. In this respect, I was trying to update the slider position each time when we press the playButton using horizontal-slider->setValue(); using a simple loop from zero to max (horizontal-slider->maximum()) and keep updating (increasing) it until we again click the playbutton.
17:25
Dev_
This is how i thought to proceed for other events also. I want to know am i On right track.
17:25
Dev_
That's it se6astian
17:25
Bertl
what does your mentor say?
17:26
Dev_
I haven't provided him this approach yet
17:26
Bertl
well, then I'd suggest you do so and he will let you know :)
17:27
se6astian
great, then you can discuss it already right after this meeting
17:27
se6astian
Fares_, your turn
17:27
Dev_
okay, se6astian thanks
17:27
Fares_
Hi all, this is about my task to implement lossless jpeg 1992 encoder core
17:29
Fares_
I did test several approaches on the fpga, these approaches will be used to test the core, I found that the best one was to used AXI DMA and write software bare metal to use it.
17:30
Fares_
In the next step I will write the code to read the images from sd card to memory, then AXI DMA initiation then write back to sd card.
17:30
Fares_
after the core is finished, I will test it with this approach.
17:31
Bertl
why not work with the AXIOM Beta setup for testing?
17:31
Fares_
I have explored several approaches as well to expand the core to include clip header, frame header and frame tail to be able to generate valid clip.
17:31
Fares_
as far as I know the usb module is not ready yet
17:31
Bertl
i.e. use the existing Arch Linux, fetch data from DDR and write it back to DDR
17:32
Bertl
this way you do not need to bother with SD related stuff and you do not need to adapt from the test setup to the Beta later
17:33
Fares_
bare metal seemed simpler, but I would like to read more about how to use it in Arch Linux, if you have links to help me in that regard it would be great.
17:33
Bertl
basically the entire AXIOM Beta documentation ...
17:34
Bertl
in any case, we should discuss this later
17:34
se6astian
thanks for the update Fares_, anything more to add?
17:35
Fares_
Ok, this would be all for now.
17:35
se6astian
great
17:35
se6astian
Nira originally asked me to share her progress because she is still in class right now
17:35
se6astian
but she just pmed me that she is here already, perfect timing
17:35
se6astian
Nira: please go ahead
17:36
Nira
Hi, until now I have been understanding the different parts of the Axiom Remote, by understanding the schematics and by checking documentation
17:37
Nira
I also checked what you have on the GitHub and did a little scheme for helping me understand how did you distribute everything.
17:39
Nira
On this last week, I have been reading a little bit more PIC32 datasheet and checking what you use on the project
17:40
Nira
I think that's all
17:41
Bertl
we should have a short chat with BAndiT1983 and se6astian regarding recent modifications of the remote prototype which are not documented in the schematics/layout yet
17:42
se6astian
thanks Nira, great
17:42
Bertl
(after the meeting or in the next few days)
17:42
se6astian
if anyone else wants to share progress, pm me now please, in the meantime I will also cover some points
17:44
se6astian
as Bertl mentioned maker faire vienna last weekend was a big success, lots and lots of people as the weather was too bad for outdoor activities
17:44
se6astian
next maker faire next weekend will be even bigger though
17:44
se6astian
last year it had ~15.000 visitors
17:44
se6astian
and from the apertus° community there will also be quite a big meeting
17:45
se6astian
we will be 6 people from brussels, austria and germany if everything works out
17:46
se6astian
in Berlin
17:46
BAndiT1983
a bit more i suppose
17:47
se6astian
other exciting news are that the AXIOM project and its hardware will be showcased in the museum of contemporary art design laboratory for a long term exhibition
17:47
se6astian
in Vienna
17:47
BAndiT1983
are we already that vintage? ;)
17:47
se6astian
I brought over the "exhibits" as they call our hardware today
17:48
se6astian
BAndiT1983: more visitors you mean?
17:48
Bertl
'contemporary' not 'history' ;-)
17:48
BAndiT1983
according to the list, we are around 7 people
17:48
BAndiT1983
have never been to a maker faire yet
17:48
Bertl
same order of magnitude!
17:49
se6astian
you will enjoy it
17:50
BAndiT1983
was attending night of museums in frankfurt on saturday, really hard to tell what is new art and which is old
17:50
se6astian
more brief updates: we started planning a new team tealk shooting
17:50
se6astian
cnc milled enclosure metal parts have been ordered for the AXIOM Beta compact enclosure and should be shipped soon
17:50
Bertl
with or without jokes?
17:51
se6astian
new flyers will arrive tomorrow just in time for bringing them to berlin: https://lab.apertus.org/M11#1427
17:52
BAndiT1983
Bertl, which topic do you mean?
17:52
se6astian
we will see how much we can pay rex to add dry british humor jokes to the "script"
17:52
Bertl
BAndiT1983: team talks
17:52
BAndiT1983
se6astian, nah, no need to, as he is already fascinated by Max and the beard
17:53
se6astian
https://www.mak.at/en musem website, design lab reopens on May 28th
17:53
se6astian
thats it from my side
17:54
se6astian
if there are no more reports we can conclude this first part of the meeting
17:54
BAndiT1983
nice, will try to visit it next time in vienna
17:54
se6astian
great
17:55
Bertl
so if there are no more reports, let's figure out a date and time for the next meeting
17:56
se6astian
is monday working out for you? should we meet an hour later maybe?
17:57
Bertl
monday is fine here, later is fine as well
17:58
aSobhy
if I'm not available can I send my progress to you se6astian ?
17:59
BAndiT1983
aSobhy, you can send it to any mentor, in case se6astian is not available too
17:59
Bertl
yes, but do not make that a habit, the purpose of those meetings is to get everybody together
17:59
se6astian
you can, best CC you primary mentor as well yes
18:00
Bertl
i.e. it's all about getting new ideas and utilizing synergies
18:01
aSobhy
just because the exams will start the next week I'll be eager to attend but It will depend on the next exam
18:02
Bertl
as I said, no problem, as long as it doesn't become a habit
18:03
aSobhy
sure it won't be a habit :D
18:03
Bertl
Nira, BAndiT1983, se6astian: got a few minutes for some 'Remote' chat?
18:03
BAndiT1983
yes
18:04
Nira
yes!
18:04
se6astian
I am about to pack the stuff for Maker faire berlin into my car and drive off
18:04
Dev_
BAndiT1983: Please check my messages during meeting also when u get time
18:04
se6astian
so I will attend only for a few minutes
18:04
aSobhy
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18:04
BAndiT1983
Dev_, have seen it, as i was already here and also checking logs regularly
18:04
Bertl
se6astian: okay, you can read up on it or I'll explain on the drive to Berlin
18:05
Dev_
okay BAndiT1983
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Dev_
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18:07
BAndiT1983
Dev_, have you evaluated how this would be used by the application? as the events should only notify about clicked buttons or moved slider in the playback control
18:07
BAndiT1983
but we need also a mechanism to synchronize playback visualization with video frame processing and preview
18:12
BAndiT1983
also don't forget about MVP, as the slider should be updated from other modules
18:13
BAndiT1983
try to create a sequence or flow diagram, which shows how playback slider will interact with other modules and vice versa
18:16
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18:16
se6astian
Bertl: se6astian: okay, you can read up on it or I'll explain on the drive to Berlin <- perfect, lets do that
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se6astian
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18:34
Fares
Bertl, are you here?
18:35
Bertl
yup
18:36
Fares
I preferred a bare metal solution as it is simpler and I have a z-turn lite which I will be able to test on it easily
18:36
Fares
is there a solution to test it with Arch Linux with my board? maybe using micro design?
18:38
Bertl
yes, the recent firmware images (SD card images) should work on your board just fine
18:38
Bertl
check with vup or anuejn for detail and if you have any problems
18:39
Bertl
to some degree it also simplifies development as you can simply load a new bitstream or modify registers from Linux without rebuilding your bare metal app
18:41
vup
Fares: you should be able to use the latest axiom-micro image from https://github.com/apertus-open-source-cinema/axiom-beta-firmware/releases
18:41
vup
which would be this one https://github.com/apertus-open-source-cinema/axiom-beta-firmware/releases/download/nightly%2F3f43acf8/axiom-micro-3f43acf8.img.xz
18:41
Bertl
for the DDR memory access, it would be great to use the high speed readers/writers we have on the Beta firmware, but of course you can use the Xilinx DMA for testing as well
18:43
Fares
I have already tested the firmware and it is working fine, as I understand, I would generate my own bitstream to my board to be used for testing, with Arch linux on the software side.
18:44
vup
i would advise against the xilinx axi dma core, as it is much harder to work with than the axihp_{reader,writer}'s of the beta, and you need to use the vivado's strange block diagrams
18:44
Fares
AXI DMA uses AXI Stream, is that the same protocol you use in the beta readers/writers to interface with core?
18:44
vup
no the beta readers/writers work a bit different
18:45
Bertl
Fares: yes, no need to pack or wrap up anything, just copy the .bit file to the Linux side (e.g. via ssh) and reinitialize the FPGA
18:45
vup
the most important difference being, that you need to provide the address yourself
18:46
vup
unfortunately you can't load the .bit file directly anymore
18:46
vup
you need to convert it using https://github.com/apertus-open-source-cinema/axiom-beta-firmware/blob/master/makefiles/in_chroot/to_raw_bitstream.py
18:46
vup
after that you can copy the resulting file to /lib/firmware
18:47
vup
and echo "name_of_.bit" > /sys/class/fpga_manager/fpga0/firmware
18:48
Bertl
it's actually not that different from how Xilinx DMA does it
18:49
Bertl
as far as I know (from the problems on the forums :)
18:49
Bertl
there are two DMA approaches used
18:49
vup
> the beta readers/writers work *a bit* different
18:49
vup
thats why i said a bit
18:49
Bertl
in one the data is provided on a fixed address, and DMA is set up from userspace
18:50
vup
axi stream has no address at all, or what do you mean?
18:50
Bertl
in the other the address is configured via AXI registers and the FPGA side bursts data into the given address range
18:50
Bertl
the latter is very similar to how the Beta readers/writers work
18:52
Fares
so in the latter the core it self is responsible to control the DMA not from the userspace correct?
18:52
Fares
itself*
18:53
Bertl
the readers and writers have a FIFO attached and basically from this point on you can treat them as stream interface
18:53
Bertl
the only care which needs to be taken is when you start or stop a transfer
18:54
lexano
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18:54
Bertl
addresses are 'generated' in the fabric (typically by an address generator)
18:54
Bertl
you can simply reuse the existing address generators and their AXI interface for userspace control
18:55
vup
don't the existing address generators assume that the image is always the same size?
18:56
Bertl
they make some assumptions yes
18:57
vup
ok, just checking, because thats the reason why i wrote my own for the micro
18:57
Fares
the one written in migen on github?
18:58
vup
https://github.com/axiom-micro/gateware/blob/master/cores/addr_gen.py ?
18:58
vup
yes
18:59
vup
although i would not recommend to use it, as it is really overly complicated and unnecessary
18:59
Fares
yes that is the one
19:00
Fares
okay I will look into more details about hp_readers/writers and Arch linux and loading bitstream
19:00
Fares
thank you Bertl and vup
19:00
Bertl
you're welcome!
19:00
Bertl
let us know if there are any problems ...
19:00
vup
one key thing about the axi_hp readers/writers is, that address and data a asynchronous from each other, thats what confused me for the longest time
19:01
Bertl
yeah, that's how the 'channels' in AMBA/AXI are designed
19:02
Bertl
adds more flexibility but also confusion :)
19:05
Fares
yeah, It doesn't seem simple :)
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19:30
Bertl
off for now ... bbl
19:30
Bertl
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Nira
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se6astian|away
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BAndiT1983
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