Current Server Time: 03:29 (Central Europe)

#apertus IRC Channel Logs

2018/03/13

Timezone: UTC


23:06
TofuLynx
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01:11
Bertl_oO
off to bed now ... have a good one everyone!
01:11
Bertl_oO
changed nick to: Bertl_zZ
03:28
rton
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05:25
supragya
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05:27
supragya
RexOrCine, my classes end today at 12:30 GMT. I will be available from around 1PM.
05:27
RexOrCine
104.
05:28
supragya
i don't understand that. sorry
05:30
RexOrCine
Message received.
05:30
supragya
:)
06:33
TofuLynx
Good morning!
06:44
rton
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06:49
Iti
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06:50
Iti
Good morning everyone :)
06:55
supragya
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07:06
se6astian|away
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07:24
RexOrCine
https://cloud.gerade.org/index.php/s/36LV4ckdTGfOu0J
07:27
se6astian
very nice!
07:27
TofuLynx_
that's awesome!
07:29
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sebix
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08:31
Bertl_zZ
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08:31
Bertl
morning folks!
08:35
se6astian
good morning!
09:46
supragya-web
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supragya
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12:06
supragya
RexOrCine, available now
12:13
supragya
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supragya
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12:17
RexOrCine
supragya: Yeah.
12:18
supragya
well.. if you would like to have a look, I am here
12:18
RexOrCine
OK. Follow me in the doc.
12:18
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12:18
supragya
okay
12:23
ArunM
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TofuLynx
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12:47
Bertl
off for now ... bbl
12:48
Bertl
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Arun__
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TofuLynx
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supragya
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15:07
BAndiT1983|away
changed nick to: BAndiT1983
15:14
ymc98
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15:15
ymc98
Should I include testbenches for qualification task 1 in my repository?
15:16
Bertl_oO
I presume you are doing the VHDL task, yes?
15:18
ymc98
yes
15:19
supragya
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15:23
ymc98
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15:23
Bertl_oO
well, you might want to get a proper IRC client :)
15:24
TofuLynx
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15:24
ymc98
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15:24
Bertl_oO
in general test benches are not required, but they are definitely a bonus when they do extensive testing (i.e. test the corner cases too)
15:25
Bertl_oO
if you want me to take a look at your VHDL code, let me know, I can do so an provide some feedback
15:27
ymc98_
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15:28
ymc98_
Sorry, really bad wifi here.
15:28
supragya
It's better to use a client than freenode web interface :)
15:29
ymc98_
Isn't it true writing testbenches for our own code is not advisable?
15:29
Bertl_oO
also always check the irc logs when you lose connection
15:29
ymc98
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15:30
BAndiT1983
writing tests is not advisable??? it's the first thing a developer should do
15:30
BAndiT1983
was often glad, that tests from colleagues revealed how the code has to be used
15:30
supragya
BAndiT1983, I need some technical help on documentation
15:31
BAndiT1983
yes?
15:31
Bertl_oO
ymc98_: well, sometimes you have to write your own test bench. if you have somebody else to write them for you, that's fine too
15:31
supragya
ie proposal.
15:31
supragya
can you have a look at doc
15:31
ymc98_
I see
15:31
BAndiT1983
supragya, am there
15:31
supragya
let me connect
15:33
supragya
also unsure what to add there
15:34
BAndiT1983
you have multiple things: pool allocator (which is also called static), reading only image data from sub-sequential frame, using downscaler to avoid de-bayering
15:35
supragya
sub-sequential frame?
15:35
BAndiT1983
i mean the frames after first one
15:35
supragya
oh
15:35
BAndiT1983
you read first fully, header + data, then you know image data offset
15:35
BAndiT1983
and following frames will be read from the offset on
15:35
supragya
fixed sized header I presume after first one?
15:35
supragya
or access to header is needed on other frames
15:36
BAndiT1983
if they are encoded, which i haven't met yet, then it's a bit different approach
15:36
supragya
are they to be tackled ?
15:36
BAndiT1983
my idea was to avoid header in other files and assume same information, at least for preview
15:36
BAndiT1983
?
15:36
supragya
if they are encoded, which i haven't met yet, then it's a bit different approach <- this
15:36
supragya
could not understand much
15:37
BAndiT1983
encoded -> compression
15:37
BAndiT1983
haven't seen any (C)DNG sequences which were compressed
15:37
BAndiT1983
have still to find the website, which provided many DNG sequences from different cameras
15:40
supragya
can you comment on the timeline? especially Phase 3. Looks okay?
15:43
BAndiT1983
have to look through it first, but a bit later, came home not long ago and have to install washing machine and dishwasher water supply
15:43
supragya
so much info I have got about your home now :)
15:43
supragya
whenever you are available... drop a comment
15:43
BAndiT1983
ok
15:44
ymc98_
I'm still have to finish i2c slave. Link to pwm controller vhdl code : https://github.com/mahesh15230/Task_1.git
15:45
ymc98_
Thanks for feedback in advance
15:57
Bertl_oO
first, Copyright is great! but you need to use your name there, otherwise it won't work
15:57
Bertl_oO
also, put it under a FOSS compatible license
15:57
Bertl_oO
regarding your question? about <= and := ...
15:57
Bertl_oO
<= assigns to signals while := assigns to variables
15:58
Bertl_oO
first thing you want to do is fix the indentation and the spaces in the code
15:59
Bertl_oO
also, you don't need/want parentheses for conditions in VHDL, so e.g. line 39 becomes:
15:59
Bertl_oO
if reset = '0' then
15:59
Bertl_oO
and line 42 becomes elsif rising_edge(clk) then
15:59
nmdis1999
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16:00
nmdis1999
Hi Bertl, when you'll be frew tomorrow?
16:00
nmdis1999
Free*
16:00
Bertl_oO
don't know, you want something reviewed or something else?
16:00
nmdis1999
I will complete my proposal tomorrow, so it'd be good if you can have a look at it.
16:01
Bertl_oO
just let me know (here) when you have something and I'll check it as soon as possible
16:02
nmdis1999
Okay, thanks
16:02
Bertl_oO
no problem
16:03
Bertl_oO
ymc98_: generics are basically constants so you want to write them all upper case (see existing code)
16:03
Bertl_oO
(same of course for real constants
16:05
Bertl_oO
ymc98_: one more hint: you proabbly want to run the code through a synthesis and implementation to check some basic stuff
16:05
Bertl_oO
-a
16:06
Bertl_oO
also please add a link to your code to the challenge task, it's easier to find
16:14
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ymc98
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16:16
ymc98
Bertl_oO : I'll do all of that. Again, thank you very much.
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felix_
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17:01
BAndiT1983
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17:01
BAndiT1983|away
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17:03
Bertl_oO
ymc98: you're welcome!
17:13
BAndiT1983
supragya, should we continue to look into your proposal?
17:14
supragya
sure...
17:14
supragya
let me connect
17:40
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sebix
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17:55
supragya
hey TofuLynx
17:58
BAndiT1983
hi TofuLynx, should we do the C++ challenge review?
17:59
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BAndiT1983
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comradekingu
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21:43
se6astian
off to bed
21:43
se6astian
good night
21:43
se6astian
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22:55
seku
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