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#apertus IRC Channel Logs

2015/03/13

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01:47
fsteinel
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fsteinel_
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intracube_
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ItsMeLenny
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07:01
fsteinel_
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08:04
Bertl_zZ
changed nick to: Bertl
08:04
Bertl
morning folks!
08:22
se6astian|away
changed nick to: se6astian
08:23
se6astian
good morning
08:27
intracube
joined the channel
08:27
Bertl
morning se6astian!
08:31
Francky
joined the channel
08:32
Francky
hi all
08:32
Francky
i saw that the cnc mill has arrived !
08:32
Francky
good news
08:32
Bertl
yup
08:33
Francky
is the beta camera case already designed ?
08:34
se6astian
no
09:05
cbohnens|away
changed nick to: cbohnens
09:11
Jin|away
changed nick to: Jin^eLD
09:25
Francky
does the pic32 board still urgent or is there something more urgent I can help for ?
09:29
Bertl
good question, the pic board is still urgent, but not that urgent I guess
09:30
Bertl
although, as you want to work on the code side as well, we should probably get the interfaces defined so that you can build one for testing
09:30
Bertl
but, IIRC, you also wanted to play with the FPGA, right?
09:44
Francky
yes
09:44
Bertl
okay, so what development kit do you have ATM?
09:44
Francky
i've got a microzed 7010 and a JTAG
09:45
Bertl
okay, a breakout board for the 7010 or similar?
09:50
Francky
breakout board ?
09:50
Bertl
something which allows you to connect the FPGA to the outside
09:52
Francky
no, unless the connectors of the microzed (etherent usb x2)
09:52
Francky
but if needed i can build a carrier board to use the bottom connector of microzed
09:52
Bertl
okay, so you might want to get one anyway, there is a simple breakout available for the microzed, or you can use this one:
09:53
Bertl
https://oshpark.com/shared_projects/n4Um27z8
09:53
Bertl
I can upload the most recent version as well, sec
09:56
Bertl
http://vserver.13thfloor.at/Stuff/AXIOM/BETA/microzed_breakout_v0.6.{sch,brd}
09:57
Bertl
but till you get the boards and build them, you can already start working on something we need
09:59
Francky
what are the purpose of this board ? i.e. : what are the types of connectors and to what can we connect them ?
09:59
Francky
i spead about X1 to X12
10:00
Francky
speak*
10:00
Bertl
the purpose is to have connections to other boards or high speed "loopback" connections to the same board (for testing)
10:01
Francky
ok
10:01
Bertl
I chose to use SATA cables for the typical board to board connection
10:01
Bertl
those are the X* connectors
10:01
Francky
ok
10:02
Francky
perfedt for LVDS signals too ?!
10:02
Bertl
and SMA for testing or scope connections, those are the X*/Y*
10:02
Francky
perfect*
10:02
Francky
yes i recognized them
10:02
Bertl
yup, all of them should allow for up to 4GHz at least, so the connections should be fine
10:03
Bertl
the PMOD connectors are the standard for extension modules on xilinx boards
10:03
Bertl
and they are realized as simple edge-solder-on connections
10:03
Bertl
so you get a 2x6 female header, stick it on the board and solder it to the contacts
10:04
Bertl
here is the latest version if you want to order it from OSHpark
10:04
Bertl
https://oshpark.com/shared_projects/mU6yxxm8
10:04
Francky
what is the lead time for oshpark ?
10:05
Bertl
depends on where you are and what you want to pay for shipping
10:05
Bertl
they usually make the 4layer boards in a week
10:05
Francky
ok
10:05
Bertl
if you go for priority shipping, you will get it in two weeks at most
10:05
Francky
and you add a ft232 to have a RS232-usb bridge
10:06
Bertl
that one is optional and not really tested (yet)
10:06
Bertl
it is a debug interface for the microzed, i.e. USB to JTAG
10:06
Francky
ok
10:07
Bertl
you can see what is connected where on the schematics
10:07
Francky
there already is one on the microzed no ?
10:07
Bertl
the microzed only has a jtag header, no usb interface for it
10:07
Francky
there is a micro usb connector which is used to debug the arm
10:07
Bertl
(that's why you got a jtag dongle :)
10:08
Bertl
the micro USB is for power and console
10:08
Bertl
(on the microzed)
10:08
Francky
ok you spoke about usb debuging for pfga side
10:08
Francky
fpga*
10:09
Bertl
yep, it is supposed to replace the JTAG dongle
10:09
Francky
ok
10:09
Bertl
so not required for you if you got one (dongle)
10:11
Bertl
so, what do we need you can do on the microzed without any breakout ...
10:12
Bertl
we plan to do extensive bandwidth testing for the FPGA-FPGA connections and that requires a testing framework
10:12
Francky
maybe some very small IP that i can implement and simulate ?!
10:13
Bertl
i.e. a design which sends out data over a high speed serial link (which is looped back) receives and verifies the same data
10:13
Bertl
I have a few components for this already, like some very nice pseudo random generators to test with
10:14
Bertl
but there needs to be synchronization as well as training
10:14
Bertl
(for the LVDS connection)
10:14
Bertl
and we want to count the error rate at a given frequency/encoding
10:16
Bertl
so, to start simple: a configureable generator which can send out a pseudo random number stream to one (or several) LVDS pairs
10:16
Bertl
(note that the bits should be interleaved when using several pairs, so that we can test crosstalk as well)
10:17
Francky
ok so i will be able to loop back the output lvds to an input lvds with the breakout board
10:17
Bertl
correct, and for testing, you can simply loop it back inside the FPGA
10:18
Bertl
(no delay, no training of course)
10:18
Francky
ok
10:18
Bertl
well, maybe you are creative and get that working as well
10:18
Bertl
but you should be able to test it in simulation
10:18
Francky
don't forget that i'm fpga beginner :)
10:19
Francky
i wil try to do something, but i have to tell you that i may have some questions...
10:19
Bertl
yes, it will be a steep path, I'm sure, so do not give up at the beginning
10:19
intracube
left the channel
10:19
Bertl
let me dig out the PRNG sources
10:26
Bertl
http://vserver.13thfloor.at/Stuff/AXIOM/BETA/prng/
10:26
Bertl
here you go, this implements three different PRNG variants
10:28
Bertl
I found out (by analysis and inspection of the data) that a simple combination (xor) of the two really fast variants (Fibonacci and Galois) give random numbers with similar quality as the complicated mersenne twister
10:28
Francky
ok so the aim is to use this prng and send the result on one or more lvds pair right ?
10:28
Bertl
basically yes
10:29
Bertl
what we need to do is the following:
10:29
Bertl
make the random sequence seeded (i.e. you can start the PRNG with a seed value)
10:29
Bertl
this allows to rerun a test with exactly the same sequence
10:30
Bertl
make the bitwidth for the data configureable (to some degree)
10:30
Bertl
e.g. powers of two or similar
10:31
Bertl
this might require several PRNG with different seeds to achieve certain bitrates
10:31
Bertl
but start with something simple you can also simulate easily
10:31
Bertl
like for example the seeding of a single PRNG
10:32
Francky
ok
10:32
Bertl
I will most likely finalize the PIC32 interface on the weekend or shortly after, so you can mix between FPGA work and board design then
10:34
Francky
fine !
10:35
Francky
first i try to understand the "package" of the prng and how to use it
10:36
Bertl
yes, that is a good start, don't get lost in the mathematics though
10:36
Francky
the dpram and rng_sr are only for interna use right ?
10:37
Bertl
correct
10:37
Francky
i don't look at "how it is working inside" but how i can connect it to outside, and what type of signals i need to put to have a number generation
10:37
Francky
i will then try to simulate this
10:37
Bertl
sounds good!
10:40
Francky
i'm not a completely novice in fpga in fact, i have got some classes when i was at the university, so i know a little bit the fpga coding, but the theory and the reality is different
10:41
Bertl
of course, and there are the tools as well
10:41
Francky
so i need to learn how to use the builder, the gui, the simulation tool...
10:41
Francky
but i'm optimistic
10:41
Francky
:)
10:42
Bertl
use whatever you like, but please, at the end, make sure that it builds at the commandline (i.e. without any magic gui files and similar)
10:43
Bertl
also I would appreciate if you could (somewhat) follow the coding style we have used for the cmv_io/hdmi
10:43
Francky
yes no problem
11:05
lab-bot
sebastian committed rBHb836ebd15e57: Merge branch 'master' of https://github.com/apertus-open-source-cinema/beta⦠(authored by sebastian).
11:05
lab-bot
daFred committed rBHcaa653f07901: Beta Skeleton (authored by daFred).
11:05
lab-bot
daFred committed rBH65ec4806084c: Beta Skeleton moved (authored by daFred).
11:05
lab-bot
sebastian committed rBH0ebaefca4171: added nikon mount 3d print part (authored by sebastian).
11:10
Francky
Bertl : what is the purpose of signals mode, s_in and s_out ?
11:10
Francky
i don't see any use of them in simulation
11:12
Bertl
the prng is part of a larger project and they are connected from the module using the prng
11:12
Bertl
mode controls shift input vs. shift output
11:13
Bertl
(to load a seed value)
11:13
Bertl
and sr_in/out is the serial input/output
11:13
Francky
ok i precisely search how to put a seed value
11:14
Bertl
the idea is, when mode=1, then you can shift new bits into the shift register via sr_in
11:14
Francky
so you put mode to 0, enter a seed value throught s_in, and put mode to 1 to start generation ?
11:14
Bertl
and the old values come out via sr_out, similar to SPI or JTAG
11:14
Francky
ok
11:15
Bertl
in mode '0' the prng operates normally
11:15
Francky
you have a 32 bit register for seed value right ?
11:15
Bertl
yes, those are 32bit PRNGs
11:15
Francky
ok
11:15
Francky
i continue to explore the simulation...
11:16
Bertl
if you later chain several of them, you can connect them via sr_in/out
11:16
Bertl
(to load longer seed values)
11:17
Francky
ok
11:18
Francky
changed nick to: Francky|eating
11:19
Bertl
bon appetit!
11:38
Francky|eating
merci ;)
12:43
Francky|eating
changed nick to: Francky
12:43
Francky
Bertl > I'm playong with the prng
12:43
Francky
i've creating a package which implement the prng
12:43
Francky
and send a seed value at the beginning
12:44
Francky
but when i simulate, the prng send a result whereas mode = 1 and CE = 0
12:44
Francky
is there something i don't understand right ?
12:44
Bertl
for simulation you need to create some stimulus
12:44
Francky
yes i've done
12:44
Francky
it is working
12:44
Bertl
okay, show me the code then :)
12:45
Francky
i had simulated the prng alone and it is working well
12:45
Francky
don't be afraid :)
12:45
Francky
how can we open a private chat between us ?
12:46
Bertl
simply by /msg <nick>
12:54
Francky
come back here
12:55
Bertl
back :)
12:56
Francky
did you saw something very foul in my code ?
12:57
Bertl
well, it is a start for testing, note that we need to connect the seed, seed upload, etc to something else, so the constant won't do
12:57
Bertl
for the MicroZed side, we will connect it somehow to the memory space to control it from the PS side
12:57
Francky
ok
12:58
Bertl
but I would suggest a more generic interface first
12:58
Bertl
like for example SPI, which can be easily implemented in the smaller FPGAs and connected to the MicroZed
12:58
Bertl
we then add an SPI controller which maps the connections to the PS
12:59
Bertl
but first, make a design what we actually need to control and measure
12:59
Bertl
(because it will shape the communication)
13:02
Bertl
basically we will see two types of communication between FPGAs: with and without a clock signal
13:03
Bertl
with a clock signal, we send a reference clock (lower or clock rate) on a separate LVDS pair
13:03
Bertl
(when I say LVDS, I generally mean differential signalling, not necessarily LVDS levels)
13:04
Bertl
without a clock signal, the receiver has to recover the clock from the mixed line
13:04
Bertl
(usually with a CDR circuitry)
13:05
Bertl
on DS it is generally a good idea to keep the DC bias somewhere in the middle
13:05
Bertl
i.e. not to send too many zeroes or ones in a row
13:05
Bertl
(that's where the encoding, e.g. 8/10, TMDS, etc) comes in
13:06
Bertl
and we need a way to communicate some limited out of band information
13:06
Bertl
like when/where the datastream starts, etc
13:10
Francky
ok so the prng block will be connected to PS through a SPI block (build in the PL) right ?
13:10
Bertl
for example
13:21
danieel
left the channel
13:22
Jin^eLD
changed nick to: Jin|away
13:23
Francky
when we write this code :
13:23
Francky
prng_inst : entity work.prng32
13:24
Francky
which architecture of prng32 is used ?
13:24
Francky
because when i choose an architecture with for example
13:24
Francky
prng_inst : entity work.prng32(LUT_SR)
13:24
Francky
it doesn't work well in the simulator
13:25
Francky
it doesn't work well with the 3 architecture, but when i don't write the architecture, it is working well
13:26
Francky
oh sorry it seems that there is 4 architecture of pnrg
13:26
Francky
the MT32 is used by default, and it is the only one which works
13:29
Bertl
LUT_SR was not updated, but the other two should work fine
13:29
Bertl
i.e. LFSR_FIB and LFSR_GAL
13:30
Bertl
and if you specify no architecture, the last one is used by default
13:30
Francky
MT32 don't take care ok mode signal
13:30
Francky
of*
13:30
Bertl
yes, I haven't investigated how to properly seed that one
13:31
Bertl
feel free to fix/implement it :)
13:31
Francky
i try to modify the code to explore
13:33
Francky
there is something i don't understand in the architecture of prng
13:33
Francky
when mode = 1, it is a shift register in fact
13:34
Francky
it take the s_in and put in the sr
13:34
Francky
whith a shift
13:34
Francky
this make the shift :
13:34
Francky
sr <= sr(30 downto 0) & s_in;
13:34
Francky
?
13:34
Francky
right ?
13:34
Bertl
correct
13:35
Bertl
LFSR stands for Liner Feedback Shift Register
13:35
Bertl
*Linear
13:36
Bertl
the mersenne twister is a little more complicated though
13:36
Bertl
i.e. it has counters and state information, etc
13:37
Francky
oh no it is ok i undestand whith the simulator
13:38
Francky
in fact i was wainting for having the seed on the s_out, but it was always to 1... but i forgot that there is the 32 bit shift register between s_in and s_out
13:40
Bertl
okay, so everything fine now?
13:47
danieel
joined the channel
13:51
Francky
not the output
13:55
aombk
μεγειά to cnc
13:56
aombk
so is it a 3 axis one?
14:00
intracube
joined the channel
14:00
lab-bot
sebastian closed T313: update sponsors and benefactors website as "Resolved". http://lab.apertus.org/T313
14:03
aombk
oh its 3 axis but can be upgraded?
14:04
Bertl
yes, and we have a 4th axis AFAIK
14:04
aombk
great
14:04
Bertl
se6astian: do you have the Tormach details somewhere online?
14:05
Bertl
i.e. what parts/features/accessories we got
14:14
Francky
Bertl : are each lines of a process are executed at the same time ?
14:16
Bertl
processes are sequential constructs, but assignments to signals happen at the end of a "run"
14:16
Francky
in fact with the simulator i see :
14:17
Francky
- that the sr of prng is great charged with the seed
14:17
Francky
but at the first clock rising after mode passed to 0, the bit 0 is marked as "U" (like unasigned I mean) ?
14:19
lab-bot
sebastian created T316: BIP SSL. http://lab.apertus.org/T316
14:20
Francky
i am using the LFSR_FIB architecture
14:20
Francky
and the fb signal is always U, unless at 1 time when it is at 1
14:21
Bertl
that might be an initialization problem, please make a wave diagram with all the involved registers and upload it somewhere
14:21
Bertl
note that vivado simulator cannot properly simulate variables
14:21
Bertl
(so make sure to have everything on signals for debugging)
14:23
se6astian
aombk: we have the 4th axis addon: http://www.tormach.com/store/index.php?app=ecom&ns=catshow&ref=multicat_8_Inch_Tables
14:24
se6astian
plus the automatic tool changer: http://www.tormach.com/store/index.php?app=ecom&ns=catshow&ref=multicat_pcnc_1100_s3_atc
14:24
se6astian
plus the small volume injection molder
14:24
se6astian
http://www.tormach.com/store/index.php?app=ecom&ns=prodshow&ref=32079
14:25
se6astian
plus pneumatic drawbar, coolant spray kit
14:26
se6astian
etc.
14:27
Jin|away
changed nick to: Jin^eLD
14:27
Francky
with an initialisation of fb to 1, it seems to work better
14:30
Francky
it is the same for the LFSR_GAL architecture
14:30
Francky
i initialise the fb to 1
14:30
Bertl
yeah, fb should be initialized
14:31
Bertl
that is a bug, please fix it and send me a patch
14:31
Francky
i've also add that the result is 0 untill mode = 1
14:31
Bertl
excellent!
14:33
Francky
but i don't know if it is a good solution i implement
14:34
Bertl
we'll see
14:34
Bertl
it's always good to make separate patches/commits per feature
14:34
cbohnens
changed nick to: cbohnens|away
14:34
Bertl
so that one can cherry pick what is perfect and what needs some work
14:35
Francky
yep
14:37
Francky
is it ok to create a process to manage the output in case of mode value ?
14:38
Francky
or is it better to use only 1 process ?
14:38
Bertl
doesn't matter how many you have, it should be readable
14:39
Bertl
I would probably implement it like this (just to give you an idea):
14:39
Bertl
after rising_edge(clk), rng <= (others => '0'); as default
14:40
Bertl
then, in the else case, at the end, rng <= sr;
14:40
Bertl
note that this will result in a one cycle delay
14:40
Francky
does the "if rising edge" needed ?
14:40
Bertl
alternatively, rng <= sr(30 downto 0) & fb;
14:41
Bertl
well, you need the clock check if you want the change to be synchronous
14:41
Bertl
you could change it asynchronously, simply by changing the
14:41
Francky
but i create a process with clk in the list of stimuli so this process will be execute at each change of clk no ?
14:42
Francky
i write this :
14:42
Francky
output : process(clk, mode)
14:42
Francky
begin
14:42
Francky
if mode = '1' then
14:42
Francky
rng <= X"00000000";
14:42
Bertl
rng <= sr; to rng <= sr when mode=1 else (others => '0');
14:42
Francky
else
14:42
Francky
rng <= sr;
14:42
Francky
end if;
14:42
Francky
end process;
14:42
Bertl
that is mostly wrong for a few reasons
14:42
Francky
i should use (others => '0')
14:43
Francky
it was my initial question : is it bad ? :)
14:43
Bertl
first, the clk is not used, so why put it on the sensitivity list
14:43
Bertl
secondly, the process will run continuously, as there is no trigger (no edge)
14:44
Bertl
so you will get similar behaviour (async) as with the "when" I pasted above
14:44
Francky
i thought that the process will be called at each change of clk
14:44
Francky
called one time
14:44
Bertl
no, a process is executed whenever one of the sensitiviy arguments changes
14:45
Bertl
so yes, it is executed on clk changes, but they have no effect
14:45
Bertl
as the toggle of mode is the controlling condition
14:45
Francky
yes ok clk shouldn't be in the sensitivity list
14:46
Francky
but in the case, the process will be execute one time at each change of mode right ?
14:46
Bertl
the disadvantage of such an asynchronous design is that you will get a lot of timing issues from that
14:46
Bertl
because mode needs to be changed _before_ the rising clock edge to register in the synchronous process
14:47
Bertl
so the value will change somewhere between the clock cycles
14:48
pgielda|away
changed nick to: pgielda
14:49
Bertl
wb pgielda!
14:49
pgielda
hi
14:49
pgielda
what a quick reaction
14:53
se6astian
hey there
14:54
pgielda
hi
14:59
Francky
Bertl > https://dl.dropboxusercontent.com/u/782577/prng.patch
14:59
Francky
tell me if it is ok for you ?
15:04
aombk
se6astian, its great you have those tools
15:05
Bertl
Francky: looks good except for the formatting of the (now) long lines
15:05
se6astian
aombk: yes I am very curious already to see the mill in full action
15:06
Bertl
and it might be better to introduce an intermediate signal for the twister
15:08
aombk
i hope i can send some models to be milled in the future to add some variation so the cnc will not get bored from milling beta bodies
15:08
Francky
for me, a twister is that -> http://fr.wikipedia.org/wiki/Tornade
15:09
Bertl
now make that with some special prime numbers, and you get the PRNG :)
15:10
Francky
what did you mean by "formatting of the long line" ? did you mean that the "when" should be place on several lines ?
15:10
Bertl
http://en.wikipedia.org/wiki/Mersenne_twister
15:10
Bertl
yes, for readability, we try to end the line around 72 characters
15:11
Francky
ok
15:11
rhavan
joined the channel
15:12
rhavan
left the channel
15:12
Francky
but in your coding chart, do you put the when statement on several lines, like the "if" statement ?
15:13
Bertl
search for a when in the cmv_io/hdmi code, I'm sure there is one or more :)
15:14
Francky
ok found ;)
15:20
Jin^eLD
changed nick to: Jin|away
15:21
Francky
https://dl.dropboxusercontent.com/u/782577/prng.patch
15:21
Francky
it should be good
15:23
Bertl
close, but no banana! the when/else needs to get some indent
15:23
Bertl
i.e. whitespace isn't perfect yet, note that the default is 8 characters per tab
15:25
Francky
in fact i took the top.vhd of the cmv_hdmi2 and took one "when" for example
15:25
Francky
but the indent is changing into the file
15:26
Francky
sometime on 3 line without indentation (like i did)
15:26
Francky
sometime one 1 line
15:26
Francky
sometime on 2 lines with indent
15:27
Bertl
this might be because your editor doesn't handle the TAB=8 correctly
15:27
Francky
so what is the "right" way ?
15:27
Bertl
double check that
15:28
Francky
you can have a look at top.vhd of cmv_hdmi2 project
15:28
Francky
line 1876 -> 3 lines without indentation
15:28
Francky
line 1885 -> 1 line
15:28
Francky
line 1891 -> 2 line with indent
15:29
Francky
no ?
15:29
Francky
no 1891 is 3 lines
15:31
Francky
is it the 72 char limit ?
15:32
Bertl
no, there is no limit, it is just easier to read
15:32
Bertl
the 1876 example has 3 lines becuase it is also easier to read
15:33
Bertl
the basic principle is to make a 4char indentation when you "continue" something
15:33
Bertl
and to keep the indentation on the same level for equivalent code
15:34
Bertl
but it is not so strict, it is more to make the code readable
15:34
Bertl
(and it is easily fixed)
15:36
Francky
ok
15:37
Francky
just to take the good practices from the beginning
15:38
Bertl
it was basically a coding style I established during the alpha software development, so nothing is set in stone and I'm open to a more formal indentation ruleset
15:38
Bertl
but so far it has proven very useful
15:41
Francky
is there a problem to use a intermediate signal ?
16:07
Bertl
depends on how you do it
16:08
Bertl
it can introduce delays in clocked designs
16:08
Bertl
(i.e. create a register)
16:08
Francky
ok
16:08
Francky
for another thing : why do you use alternatively CMS and throught hole sata connectors on the microzed breakout board ?
16:09
Francky
surface mount*
16:10
Bertl
hehe, that is a good question :)
16:10
intracube
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16:10
Bertl
I did this because not everybody has a way to reflow the board
16:10
se6astian
changed nick to: se6astian|away
16:10
Bertl
so those folks who are not able to easily solder on the SMT version, can work with the THT ones
16:10
Francky
but why don't use only throught hole connectors ?
16:11
Bertl
because the SMT version is way faster for those who have a way to reflow :)
16:11
Bertl
but yeah, I could have gone either way, the mix was probably because I couldn't decide for one :)
16:12
Francky
nothing is left to chance with you :)
16:13
Bertl
sometimes I tend to overthink things, so it's not always a blessing ...
16:16
Francky
molex sata connectors will be good for the board ?
16:16
Bertl
yes, they should be, let me check what models I got
16:18
intracube
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16:23
Bertl
the 67800 series should be fine, but please double check with the footprint, I've used some existing connectors here
16:25
Bertl
so that would be: 67800-5022 and 67800-8115
16:32
Francky
this is the references you use right ?
16:41
Bertl
those are the molex part numbers which I consider appropriate
16:42
Bertl
but I just checked, I used connectors of unknown origin here, which worked fine, so no guarantee that they are those types
16:44
Francky
ok i will check thank you
16:47
Francky
i will order all i need at the beginning of next week :)
16:49
pgielda
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16:53
Francky
bye
17:00
Francky
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18:08
Francky|busy
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18:08
Francky|busy
Hey Bertl
18:08
Bertl
hey
18:09
Francky|busy
I thought about the breakout board for microzed
18:10
Francky|busy
Did you choose the lvds pairs connected to the sata connector to be able to connect a `sata sensor board`
18:10
Francky|busy
Which could be a board similar to the breakout one
18:10
Francky|busy
With a sensor on one side and sata connector on the other side
18:10
Bertl
yes, there are always LVDS pairs on each connector and they have a consistant scheme
18:11
Francky|busy
It could be a rich idea to build a `cheap` dev board to play with the sensor no?
18:12
Bertl
well, we have the beta boards, which basically is that connection
18:12
Bertl
the dummy interface and the current test Beta will allow to connect 32 of the 64 LVDS channels
18:12
Francky|busy
But the beta board need also the power board and the interface board no?
18:13
Bertl
yes and no, you can get away without the power board
18:13
Bertl
(you still need external power)
18:13
Bertl
and the interface board is available as dummy
18:13
Bertl
i.e. just a connection for those 32 LVDS channels
18:13
Bertl
basically replaces 16 SATA cables :)
18:14
Bertl
or 18 to be precise :)
18:16
Francky|busy
Why don't you let the possibility to connect directly the microzed to the interface board?
18:17
Bertl
that was what we planned with the original Beta, but it has some major drawbacks compared to the current design
18:17
Bertl
but you can still do that if you like
18:17
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18:18
Francky|busy1
Ok
18:18
Francky|busy1
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18:19
Francky|busy1
That was my evening thoughtâ¦
18:19
Francky|busy1
Thanks for answers
18:19
Francky|busy1
I need to go
18:19
Bertl
you're welcome!
18:19
Francky|busy1
Bye
18:19
Bertl
cya
18:19
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18:49
lab-bot
BAndiT1983 created T317: Define core. http://lab.apertus.org/T317
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lab-bot
BAndiT1983 created T318: Evaluate logging frameworks. http://lab.apertus.org/T318
20:22
fadro
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20:23
fadro
good evening!
20:25
fadro
well i found some time to go on with the Beta's diagrams
20:26
fadro
you'll find the repository here: https://www.dropbox.com/s/lz5qejsft1sqmhp/diagrams.tar?dl=0
20:34
fadro
bye
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20:39
Bertl
that was quick :)
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lab-bot
BAndiT1983 created T319: Create unified theme. http://lab.apertus.org/T319
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intracube_
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21:21
Bertl
off for a nap ... bbl
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Bertl
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