#apertus IRC Channel Logs

i saw that the cnc mill has arrived !

yup

no

good question, the pic board is still urgent, but not that urgent I guess

but, IIRC, you also wanted to play with the FPGA, right?

okay, so what development kit do you have ATM?

okay, a breakout board for the 7010 or similar?

something which allows you to connect the FPGA to the outside

but if needed i can build a carrier board to use the bottom connector of microzed

https://oshpark.com/shared_projects/n4Um27z8

http://vserver.13thfloor.at/Stuff/AXIOM/BETA/microzed_breakout_v0.6.{sch,brd}

what are the purpose of this board ? i.e. : what are the types of connectors and to what can we connect them ?

speak*

ok

those are the X* connectors

perfedt for LVDS signals too ?!

perfect*

yup, all of them should allow for up to 4GHz at least, so the connections should be fine

and they are realized as simple edge-solder-on connections

here is the latest version if you want to order it from OSHpark

what is the lead time for oshpark ?

they usually make the 4layer boards in a week

if you go for priority shipping, you will get it in two weeks at most

that one is optional and not really tested (yet)

ok

there already is one on the microzed no ?

there is a micro usb connector which is used to debug the arm

the micro USB is for power and console

ok you spoke about usb debuging for pfga side

yep, it is supposed to replace the JTAG dongle

so not required for you if you got one (dongle)

we plan to do extensive bandwidth testing for the FPGA-FPGA connections and that requires a testing framework

i.e. a design which sends out data over a high speed serial link (which is looped back) receives and verifies the same data

but there needs to be synchronization as well as training

and we want to count the error rate at a given frequency/encoding

(note that the bits should be interleaved when using several pairs, so that we can test crosstalk as well)

correct, and for testing, you can simply loop it back inside the FPGA

ok

but you should be able to test it in simulation

i wil try to do something, but i have to tell you that i may have some questions...

http://vserver.13thfloor.at/Stuff/AXIOM/BETA/prng/

I found out (by analysis and inspection of the data) that a simple combination (xor) of the two really fast variants (Fibonacci and Galois) give random numbers with similar quality as the complicated mersenne twister

basically yes

make the random sequence seeded (i.e. you can start the PRNG with a seed value)

make the bitwidth for the data configureable (to some degree)

this might require several PRNG with different seeds to achieve certain bitrates

like for example the seeding of a single PRNG

I will most likely finalize the PIC32 interface on the weekend or shortly after, so you can mix between FPGA work and board design then

first i try to understand the "package" of the prng and how to use it

the dpram and rng_sr are only for interna use right ?

i don't look at "how it is working inside" but how i can connect it to outside, and what type of signals i need to put to have a number generation

sounds good!

of course, and there are the tools as well

but i'm optimistic

use whatever you like, but please, at the end, make sure that it builds at the commandline (i.e. without any magic gui files and similar)

yes no problem

daFred committed rBHcaa653f07901: Beta Skeleton (authored by daFred).

sebastian committed rBH0ebaefca4171: added nikon mount 3d print part (authored by sebastian).

i don't see any use of them in simulation

mode controls shift input vs. shift output

and sr_in/out is the serial input/output

the idea is, when mode=1, then you can shift new bits into the shift register via sr_in

and the old values come out via sr_out, similar to SPI or JTAG

in mode '0' the prng operates normally

yes, those are 32bit PRNGs

i continue to explore the simulation...

(to load longer seed values)

merci ;)

Bertl > I'm playong with the prng

and send a seed value at the beginning

is there something i don't understand right ?

yes i've done

okay, show me the code then :)

don't be afraid :)

simply by /msg <nick>

back :)

well, it is a start for testing, note that we need to connect the seed, seed upload, etc to something else, so the constant won't do

ok

like for example SPI, which can be easily implemented in the smaller FPGAs and connected to the MicroZed

but first, make a design what we actually need to control and measure

basically we will see two types of communication between FPGAs: with and without a clock signal

(when I say LVDS, I generally mean differential signalling, not necessarily LVDS levels)

(usually with a CDR circuitry)

i.e. not to send too many zeroes or ones in a row

and we need a way to communicate some limited out of band information

ok so the prng block will be connected to PS through a SPI block (build in the PL) right ?

when we write this code :

which architecture of prng32 is used ?

prng_inst : entity work.prng32(LUT_SR)

it doesn't work well with the 3 architecture, but when i don't write the architecture, it is working well

the MT32 is used by default, and it is the only one which works

i.e. LFSR_FIB and LFSR_GAL

MT32 don't take care ok mode signal

yes, I haven't investigated how to properly seed that one

i try to modify the code to explore

when mode = 1, it is a shift register in fact

whith a shift

sr <= sr(30 downto 0) & s_in;

right ?

LFSR stands for Liner Feedback Shift Register

the mersenne twister is a little more complicated though

oh no it is ok i undestand whith the simulator

okay, so everything fine now?

not the output

so is it a 3 axis one?

sebastian closed T313: update sponsors and benefactors website as "Resolved". http://lab.apertus.org/T313

yes, and we have a 4th axis AFAIK

se6astian: do you have the Tormach details somewhere online?

Bertl : are each lines of a process are executed at the same time ?

in fact with the simulator i see :

but at the first clock rising after mode passed to 0, the bit 0 is marked as "U" (like unasigned I mean) ?

i am using the LFSR_FIB architecture

that might be an initialization problem, please make a wave diagram with all the involved registers and upload it somewhere

(so make sure to have everything on signals for debugging)

plus the automatic tool changer: http://www.tormach.com/store/index.php?app=ecom&ns=catshow&ref=multicat_pcnc_1100_s3_atc

http://www.tormach.com/store/index.php?app=ecom&ns=prodshow&ref=32079

etc.

with an initialisation of fb to 1, it seems to work better

i initialise the fb to 1

that is a bug, please fix it and send me a patch

excellent!

we'll see

yep

or is it better to use only 1 process ?

I would probably implement it like this (just to give you an idea):

then, in the else case, at the end, rng <= sr;

does the "if rising edge" needed ?

well, you need the clock check if you want the change to be synchronous

but i create a process with clk in the list of stimuli so this process will be execute at each change of clk no ?

output : process(clk, mode)

if mode = '1' then

rng <= sr; to rng <= sr when mode=1 else (others => '0');

rng <= sr;

end process;

i should use (others => '0')

first, the clk is not used, so why put it on the sensitivity list

so you will get similar behaviour (async) as with the "when" I pasted above

called one time

so yes, it is executed on clk changes, but they have no effect

yes ok clk shouldn't be in the sensitivity list

the disadvantage of such an asynchronous design is that you will get a lot of timing issues from that

so the value will change somewhere between the clock cycles

wb pgielda!

what a quick reaction

hi

tell me if it is ok for you ?

Francky: looks good except for the formatting of the (now) long lines

and it might be better to introduce an intermediate signal for the twister

for me, a twister is that -> http://fr.wikipedia.org/wiki/Tornade

what did you mean by "formatting of the long line" ? did you mean that the "when" should be place on several lines ?

yes, for readability, we try to end the line around 72 characters

but in your coding chart, do you put the when statement on several lines, like the "if" statement ?

ok found ;)

https://dl.dropboxusercontent.com/u/782577/prng.patch

close, but no banana! the when/else needs to get some indent

in fact i took the top.vhd of the cmv_hdmi2 and took one "when" for example

sometime on 3 line without indentation (like i did)

sometime on 2 lines with indent

so what is the "right" way ?

you can have a look at top.vhd of cmv_hdmi2 project

line 1885 -> 1 line

no ?

is it the 72 char limit ?

the 1876 example has 3 lines becuase it is also easier to read

and to keep the indentation on the same level for equivalent code

(and it is easily fixed)

just to take the good practices from the beginning

but so far it has proven very useful

depends on how you do it

(i.e. create a register)

for another thing : why do you use alternatively CMS and throught hole sata connectors on the microzed breakout board ?

hehe, that is a good question :)

I did this because not everybody has a way to reflow the board

so those folks who are not able to easily solder on the SMT version, can work with the THT ones

because the SMT version is way faster for those who have a way to reflow :)

nothing is left to chance with you :)

molex sata connectors will be good for the board ?

so that would be: 67800-5022 and 67800-8115

those are the molex part numbers which I consider appropriate

ok i will check thank you

Hey Bertl

I thought about the breakout board for microzed

Which could be a board similar to the breakout one

yes, there are always LVDS pairs on each connector and they have a consistant scheme

well, we have the beta boards, which basically is that connection

But the beta board need also the power board and the interface board no?

(you still need external power)

i.e. just a connection for those 32 LVDS channels

or 18 to be precise :)

that was what we planned with the original Beta, but it has some major drawbacks compared to the current design

Ok

Thanks for answers

you're welcome!

cya

BAndiT1983 created T317: Define core. http://lab.apertus.org/T317

well i found some time to go on with the Beta's diagrams

bye

that was quick :)