Current Server Time: 04:47 (Central Europe)

#apertus IRC Channel Logs

2019/07/12

Timezone: UTC


02:45
Bertl_oO
off to bed now ... have a good one everyone!
02:45
Bertl_oO
changed nick to: Bertl_zZ
05:48
BAndiT1983|away
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06:16
Kjetil
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Kjetil
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06:57
Y_G
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07:13
BAndiT1983
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07:45
Umori
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Umori
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08:24
se6astian|away
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08:25
se6astian
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se6astian
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09:07
apurvanandan[m]
Hi Bertl, is there any way by which I can simulate both the FPGAs together?
09:07
apurvanandan[m]
Things don't seem to work on hardware at the moment :/
09:47
Bertl_zZ
changed nick to: Bertl
09:47
Bertl
morning folks!
09:54
futarisIRCcloud
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09:56
Bertl
apurvanandan[m]: well, you can generate the post implementation verilog for both FPGAs with timing annotation (important) and connect them as separate units
09:56
Bertl
then simulate them e.g. via Ikarus Verilog or some other simulator
10:02
hannes85
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10:22
apurvanandan[m]
Ok great!
10:24
Bertl
btw, how did you test on hardware and what didn't work?
10:24
apurvanandan[m]
Using my Virtex 5 FPGA
10:26
apurvanandan[m]
DDR x4 gearing is working correctly, Ling training is not working properly.
10:26
apurvanandan[m]
Link*
10:28
apurvanandan[m]
As When I send symmetric codes, like 1010101010 I am able to sample them. So I am trying to debug the 8 to 10 gearing and link trianing also.
10:28
apurvanandan[m]
Currently only trying with two LVDS connection: clock and one data lane
10:30
apurvanandan[m]
Also can we use single IOs for notifing the Zynq that link is trained and send real data now?
10:36
Bertl
you can, but you need to make sure that the bank voltages are the same
10:37
apurvanandan[m]
On virtex I have 2.5V, I think MachXO2 also has GPIOs at 2.5V?
10:38
Bertl
depends on what you connect there?
10:38
Bertl
i.e. you need to power the MachXO2 I/O bank
10:40
apurvanandan[m]
How we do power that?
10:43
Bertl
VCCIO is for the LVDS GPIOs (should be 2V5) and VCC for everything else (should be 3V3)
10:44
Bertl
i.e. on the breakout, everything on the yellow headers will be VCCIO
10:44
apurvanandan[m]
Ok That I have already done!
10:45
Bertl
if you use the setup we discussed last time, you should be at 2V5 for the LVDS/yellow headers
10:45
apurvanandan[m]
I think red headers
10:46
apurvanandan[m]
Yes I am using the same setup
10:46
Bertl
yes, power goes to the red headers :)
10:54
apurvanandan[m]
And yes I am currently testing this at 300MHz ie 600MBps
10:57
apurvanandan[m]
Bertl: You once said that the BER should be low as 10^-20. Is the unit here number of error bits per carrior to noise ratio(dB)?
11:03
Bertl
BER is always 'bad bits' per 'transmitted bits'
11:04
apurvanandan[m]
Okay
11:04
Bertl
i.e. the the number of bit errors divided by the total number of transferred bits
11:06
Bertl
10^-14 to 10^-16 is probably fine, 10^-20 will be hard to test
11:09
apurvanandan[m]
Okay (will have to two 64 bit counters then)
11:11
Bertl
depends on how often you read them out, but yes, 64bit counters are a good idea
11:12
apurvanandan[m]
:)
11:12
Bertl
(i.e. overflow is not a problem if your read out interval is shorter than the full counter size)
11:23
Bertl
off for now ... bbl
11:23
Bertl
changed nick to: Bertl_oO
12:45
se6astian
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12:46
se6astian|away
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13:02
se6astian
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13:04
se6astian|away
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13:06
se6astian
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13:59
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aombk
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14:15
se6astian|away
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16:05
se6astian
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jhlink
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jhlink
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17:30
BAndiT1983|away
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17:32
hannes85
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17:45
BAndiT1983
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18:01
se6astian|away
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18:38
RexOrCine|away
changed nick to: RexOrCine
18:39
RexOrCine
American Megatrends.
18:46
se6astian
the solid constant of decades of low resolution information indeed
18:50
RexOrCine
Low resolution information maybe, but high resolution fun.
19:23
Y_G
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20:11
illwieckz
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21:01
se6astian
off to bed
21:02
se6astian
good night
21:02
se6astian
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22:36
Y_G
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22:57
RexOrCine
Bertl: Ping me
23:01
RexOrCine
See 22:50 - https://www.youtube.com/watch?v=fYUwzjs8lwo ... and what he said at 23:28 about CPLD related code. To my knowledge we didn't receive anything. Is this correct? And would it help if we chased them up for it?
23:06
RexOrCine
Did you know they made 170 AXIOM Betas by mid 2017?
23:07
RexOrCine
So cripes knows how many they've made now.
23:09
Bertl_oO
RexOrCine: ping :)
23:10
Bertl_oO
Yes, I know that they made more than 150 cameras based on the Axiom Beta design, you should know as well :)
23:10
RexOrCine
I do now.
23:13
RexOrCine
So did we get the code and would it help us?
23:15
Bertl_oO
Marvx was hanging around for some time on IRC
23:16
RexOrCine
https://github.com/apertus-open-source-cinema/axiom-beta-firmware/tree/fullstack
23:17
RexOrCine
Oh
23:20
RexOrCine
I had their GitHub acct linked to on Case Studies and now it doesn't seem to be there.
00:35
RexOrCine
changed nick to: RexOrCine|away