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#apertus IRC Channel Logs

2014/06/12

Timezone: UTC


02:12
Bertl
off to bed now ... have a good one everyone!
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ApertusWeb3
changed nick to: JasonEE
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JasonEE
Joined per suggestion by Bertl
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10:48
Bertl
morning folks!
10:49
Bertl
hello JasonEE!
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13:35
JasonEE
Other IRC window locked up - was in background compiling/coding earlier when I was addressed.
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20:30
skinkie
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20:30
skinkie
hi Bertl
20:50
skinkie
Bertl: are you online?
20:55
Bertl
yep
20:57
Bertl
hey, how's going?
20:57
skinkie
i am wasting about 10GB of my SSD
20:57
skinkie
guess what I am installing ;)
20:58
Bertl
can't be vivado, as it uses way more than 10GB :)
20:58
skinkie
it is, but with a lot of options ticked off
20:58
skinkie
I am attempting something which I wonder could work
20:59
skinkie
currently I have tried the xillinux-eval-microzed stuff
20:59
skinkie
basically the bootpart in combination with something *undefined* else ;)
20:59
Bertl
okay
20:59
skinkie
but the board complains: ** Unable to read file xillydemo.bit **
21:00
Bertl
the board?
21:01
skinkie
MicroZed over minicom
21:01
Bertl
on the console, so the bootloader?
21:01
skinkie
yes
21:01
skinkie
or mostlikely the thing before/after it
21:02
Bertl
hmm, maybe capture the console output from the beginning and upload it somewhere? (pastebin)
21:03
skinkie
http://pastebin.com/q2yQZ6wq
21:03
skinkie
i am doing something that is not recommended
21:03
skinkie
but my initial question is, do i need a bitstream at all
21:04
Bertl
ah, that looks more like you have already booted a kernel
21:04
Bertl
and the kernel is trying to push the bitstream into the reconfiguration device
21:05
Bertl
this can fail for many reasons, one being the format of the file, another the permissions
21:05
skinkie
the file is not there
21:05
skinkie
and i am mixing two distributions
21:05
skinkie
because i didn't know how to make the 'boot' part of the MicroZed
21:06
skinkie
boot.bin, devicetree.dtb
21:06
Bertl
okay
21:06
skinkie
so i copied those from the xillinux stuff
21:06
Bertl
I see
21:06
skinkie
and used an uImage from somewhere else
21:06
Bertl
mix and match (or mismatch :)
21:07
skinkie
but basically the point is, is there a discription somewhere how you could make the boot.bin and devicetree.dtb
21:07
Bertl
well, have you done some basic research how the zynq boot works?
21:08
skinkie
only up to the alternative booting methods using either uboot (on the console) and the dipswitches on the board itself
21:08
skinkie
and I guess you are pointing "before that"
21:09
Bertl
okay, so the basic boot sequence is like this:
21:09
Bertl
a 'zero level' bootloader is activated as soon as the device powers on
21:09
Bertl
at this stage the jumpers (config inputs) are sampled and stored
21:10
Bertl
and this bootloader (from rom) starts to retrieve 'blocks' from a given device into the core memory area
21:10
skinkie
the zero level bootloader is something that does not change?
21:11
Bertl
yes
21:11
Bertl
once that is finished, control is handed over to the loaded fsbl (first stage boot loader)
21:11
skinkie
and uBoot can be such bootloader?
21:12
Bertl
which has to either configure the chip and external hardware or find some way to load/get more stuff
21:12
Bertl
(or both :)
21:12
Bertl
no, actually uboot is the second stage bootloader
21:12
skinkie
what is voor the zynq device the implementation of choice?
21:12
Bertl
the first stage bootloader is typically a binary blob generated by the xilinx tools
21:13
skinkie
now i wonder if Andrey implemented a fsbl or a ssbl
21:13
Bertl
the elphel folks are working on a 'free and open' fsbl for some zynq platforms, so you might want to look into that
21:14
Bertl
the problem is mostly to get the PS attached DDR memory running so that you can load more data
21:14
Bertl
the core memory is 128k (IIRC), so the fsbl has to fit there
21:15
Bertl
http://www.wiki.xilinx.com/Build+FSBL (this is the official, how to build the FSBL)
21:16
Bertl
note that while the FSBL usually includes a bitstream, it is not strictly necessary, although it makes sense to start with a sane default
21:16
Bertl
the main part of the FSBL is getting all the necessary PS parts working
21:17
Bertl
the device tree can also be generated with the tools, but I crafted my own device tree for the alpha, and it probably makes sense to do the same for the beta (which shouldn't be that different)
21:18
Bertl
ug585 covers the boot process in chapter six in some detail
21:19
skinkie
have you used the xilinx tools for this?
21:19
Bertl
for generating the FSBL, yes, for the devicetree, I used vi :)
21:20
skinkie
you are using vi to alter a binary file?
21:20
skinkie
aka devicetree.dtb?
21:20
Bertl
the dts, which can be 'compiled' into a dtb
21:20
Bertl
(you can also convert the dtb back into a dts)
21:21
Bertl
once a generic FSBL has been built, you can combine it with arbitrary uBoot versions, so there was no need yet to regenerate it (yet)
21:21
Bertl
-yet
21:21
skinkie
so basically you are saying: if you want to know the boot process, you should follow the Xilinx wiki steps
21:22
skinkie
document / script that for the Apertus situation
21:22
Bertl
either that or use/adapt the FSBL from the elphel folks
21:23
Bertl
for our purpose, the FSBL doesn't need to do much after all
21:24
Bertl
the boot.bin is generated from the FSBL (elf) plus an optional bitstream plus the uboot (elf)
21:25
Bertl
(this is done via the bootgen tool)
21:26
skinkie
i want to get this part to work :)
21:27
skinkie
i am on it :)
21:27
Bertl
so my suggestion for you is the following:
21:27
Bertl
first, use the xilinx FSBL, because it should be simple to build and utilize
21:27
Bertl
once that works, try to replace it with a modified version of the elphel FSBL
21:28
Bertl
if that (mostly) works, try to fix it until it works, if it fails horribly, delay it till we have some time/manpower for this part
21:29
Bertl
http://pastebin.com/gGUJn0S6
21:29
Bertl
bootgen -image bootimage.bif -o i boot.bin
21:30
Bertl
the u-boot.elf is the 'u-boot' file generated when building u-boot
21:30
skinkie
could you elabarote on what app_cpu1.elf is?
21:30
Bertl
the that is whatever you want to run on cpu1 (if there is anything)
21:31
skinkie
in the practical sense
21:31
Bertl
cpu0 will run the fsbl and later u-boot
21:31
skinkie
ah, so basically what should run on cpu1 when fsbl and u-boot are running, as a completely seperate processing unit?
21:31
Bertl
typically you want to keep the second core stopped or something like that if you want to go for smp later
21:32
skinkie
what example application would choose something else?
21:32
Bertl
if you use one cpu for bare metal for example
21:32
se6astian
time for bed, gnight!
21:32
se6astian
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21:32
Bertl
or if you want to run different operating systems side by side
21:32
Bertl
like two linux kernels, one for android and one for linux
21:33
skinkie
i kind of understand the application for bitstream loading in the fsbl now
21:33
skinkie
if you have a bare metal program you may just want to have everything taken care for you
21:33
Bertl
yes, it is required if you are bare metal only
21:34
Bertl
it also makes a lot of sense for our case to have a sane default
21:34
Bertl
e.g. set certain pullups or pulldowns, etc
21:34
skinkie
the files amp_fsbl and you app_cpu1.elf
21:35
Bertl
flash a led till the real stream is up and running, etc
21:35
skinkie
are they generated by the xilinx tools, or do you have them somewhere laying around?
21:35
Bertl
they have been generated once, but I never changed them since
21:36
skinkie
can you also imagine a situation where we go for a bare metal camera?
21:36
Bertl
it might make perfect sense for some applications, but I wouldn't spend extensive thought on it right now
21:37
skinkie
lets say the elphel fsbl basically stated in the readme that they don't support bitstream loading at this moment
21:37
skinkie
so thinking out loud :)
21:37
Bertl
yes, which isn't that critical atm :)
21:37
Bertl
I expect more complications with the DDR memory
21:38
Bertl
for uboot to be useable to boot linux, you need some DDR setup already in place
21:39
Bertl
and IIRC, the FSBL does some tuning there, which is basically device dependant
21:40
Bertl
that's why I think that for a start it's probably the simplest to build one (or maybe two) xilinx FSBLs for the two microzeds we might encounter in the wild
21:40
skinkie
your point are very clear to me
21:40
Bertl
and simply provide them 'as is' for combining with other elf files via bootgen
21:41
skinkie
+s
21:42
Bertl
for uboot, I think the important config areas are: networking, dhcp/bootp, tftp, simple access to all the flash and memory, fat read/write access for changing the boot files via uboot
21:43
skinkie
is uboot still limited to fat only?
21:43
Bertl
note that I went with the digilent version of uboot because the xilinx and mainstream version had terrible network performance
21:43
Bertl
nah, but for folks to update a bunch of files on the SD, it is probably simpler to have a fat partition
21:44
Bertl
because it can be accessed from linux, mac and windows easily
21:44
skinkie
yeah 'the folks that run osx' ;)
21:48
skinkie
ok thanks :)
21:48
Bertl
you're welcome!
21:48
skinkie
btw, since you suggested 'nothing could go wrong'
21:49
skinkie
if i am booting uboot from SD then indeed nothing can go wrong
21:49
skinkie
and indeed when the flashing fails of the internal memory fails, you can still boot from SD
21:49
Bertl
even if you boot it from flash, there is no permanent problem
21:50
skinkie
this is a great distinction between the embedded boards i was using before
21:50
Bertl
you can always use the jtag boot to fix it
21:50
skinkie
jtag is not fun ;)
21:50
Bertl
note that we will have jtag via USB on the Beta board
21:50
skinkie
ah thats a nice featur
21:51
Bertl
for now, do you have a suitable programmer?
21:51
Bertl
(for the microzed, I mean)
21:51
skinkie
i'll not use an unbuffered one on this board
21:52
Bertl
I can recommend this one: http://dangerousprototypes.com/wp-content/media/2011/12/jtag3.jpg
21:52
Bertl
it is simple, and cheap, and works for xilinx and altera
21:52
Bertl
(with the xilinx/altera tools that is :)
21:54
skinkie
any recommendation for an european based shop selling them?
21:54
Bertl
note that you still need a 'special' cable for the fine pitch (2mm) conenctor on the microzed
21:54
skinkie
http://nl.farnell.com/digilent/jtag-hs2/prog-cable-jtag-for-xilinx-fpga/dp/2211775 <-
21:55
Bertl
yep, should work fine as well I guess
21:56
skinkie
i am really sick/tired of the stuff customs pulls me each time
21:56
skinkie
so i rather have something from farnell where i know what i pay, then all kind of costs afterwards
21:56
Bertl
fair enough!
21:59
skinkie
i'll let you know my progress probably before tuesday
22:00
Bertl
okay, great! If you have more questions, just email me or check IRC
22:01
skinkie
will do :) good night
22:02
skinkie
(time much better spend than watching a soccergame) ;)
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23:58
Bertl
off to bed now ... have a good one everyone!