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#apertus IRC Channel Logs

2019/04/12

Timezone: UTC


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comradekingu
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Bertl_oO
off to bed now ... have a good one everyone!
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Bertl_oO
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BAndiT1983|away
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BAndiT1983
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se6astian
good day
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vup2
good morning
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Bertl_zZ
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12:03
Bertl
morning folks!
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BAndiT1983|away
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comradekingu
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BAndiT1983
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18:41
Y_G
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18:43
Y_G
Hi , the mat4_conf.sh file is only used to set the specific value for each register ,Could someone point me to where the actual color correction happens
18:44
Y_G
^ In which script does this happen "https://wiki.apertus.org/index.php/Matrix_Color_Conversion"
18:55
vup2
Y_G: do you mean where these values are used?
18:55
vup2
that happen in the fpga
18:55
vup2
here https://github.com/apertus-open-source-cinema/axiom-beta-firmware/blob/master/peripherals/soc_main/color_matrix.vhd
18:56
vup2
s/happen/happens/
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BAndiT1983|away
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19:00
Y_G
Ahh,now it makes sense ,Thanks
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19:42
vup2
great
20:12
aombk
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20:16
vup2
Bertl: do you know if any registers have to be setup and know the base address of an axi slave in the fpga, or does connecting one to a master port on ps7 block just work
20:19
Bertl
there are two slave ports at 0x40000000 and 0x60000000 and two master ports ... as far as I know they do not need any register setup to work
20:23
vup2
wait
20:23
vup2
i thought the master ports are the one at 0x{4,6}0000000
20:24
vup2
*ones
20:24
vup2
(what i mean is the master lies in the fpga and the cpu is the slave in this case)
20:24
Bertl
well, it depends on the perspective
20:25
Bertl
there are two ports which can act as AXI master and two which act as AXI slaves on the FPGA side
20:25
vup2
yes (ignoring the HP ports i guess)
20:26
Bertl
yup
20:26
vup2
ok so is the 0x{4,6}0000000 configurable or fixed?
20:27
Bertl
those are fixed as far as I know
20:27
Bertl
i.e. each port corresponds to one address range
20:28
Bertl
hey are also limited to 600MBps throughput IIRC
20:28
vup2
ah yes finally found the relevant section the the TRM
20:29
vup2
yes they seem to be fixed and seem to be at 0x{4,8}0000000
20:29
Bertl
(further) address decoding needs to be done in the FPGA
20:29
vup2
600MBps should be enough for some control stuff
20:29
Bertl
s/8/6/ 0x80000000 is memory
20:30
vup2
well the TRM says 0x8000_0000 to 0xBFFF_FFFF is the M_AXI_GP1 port
20:30
Bertl
yes, definitely sufficient for control
20:30
vup2
> (further) address decoding needs to be done in the FPGA
20:30
vup2
yes ofcourse, thats fine
20:30
vup2
is was more worried i would have to rebuild the fsbl everytime i want to change the base address
20:31
vup2
(page 112 of https://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf ) if you want to check for yourself
20:32
Bertl
indeed, my fault
20:33
Bertl
probably because we decided to map registers starting at 6000_0000
20:34
vup2
yeah, no problem, wouldn't be the first time documentation is wrong
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BAndiT1983
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BAndiT1983|away
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20:47
Bertl
off for now ... bbl
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Bertl
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se6astian
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BAndiT1983
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BAndiT1983|away
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BAndiT1983
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