| 01:40 | aSobhy | could you explain what it means by "the data word can be adjusted(bitslip)".
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| 01:40 | aSobhy | Is the out word(output) size can be changed through the process ?
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| 01:43 | aSobhy | ex : the out words of the parallel in terms of size can be a sequence like that 8b-8b-8b-10b-8b-8b-12b-12b-.....
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| 01:43 | aSobhy | <<VHDL task1>>
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| 01:44 | aSobhy | Or it can be adjusted from the beginning ?
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| 01:45 | Bertl | there is a serial stream of data, basically a sequence of zeros and ones
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| 01:45 | Bertl | 001000101111010010010010011101000100101001
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| 01:45 | Bertl | now let's say this is 8bit data
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| 01:46 | aSobhy | ok
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| 01:46 | Bertl | 00100010|11110100|10010010|...
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| 01:46 | Bertl | might be one interpretation
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| 01:47 | Bertl | 0|01000101|11101001|00100100|...
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| 01:47 | Bertl | another one
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| 01:47 | Bertl | i.e. we do not know where the stream starts or stops without further information
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| 01:48 | Bertl | to adjust for this once we have that information a mechanism called 'bitslip' is typically used
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| 01:49 | Bertl | which basically adjusts the data by one bit
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| 01:49 | Bertl | (or more precisely on a bit level)
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| 01:50 | Bertl | for example if you know your 'data' looks like this: 11110000 you can take a bitstream like this:
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| 01:50 | Bertl | 1110000111100001111000011110
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| 01:50 | Bertl | break it down into 8bit packets (i.e. deserialize it)
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| 01:51 | Bertl | 11100001|11100001|11100001|1110000
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| 01:51 | Bertl | detect that you are not at the correct bit position
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| 01:51 | Bertl | and shift it by one (or seven) bits
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| 01:51 | Bertl | till you get
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| 01:52 | aSobhy | so i need to sync
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| 01:52 | aSobhy | got it :)
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| 01:52 | Bertl | 11110000|11110000|11110000|11110000
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| 01:54 | aSobhy | but how i will sync. with 10bit or the 12bit !
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| 01:55 | aSobhy | i will drop the seven bits to sync. from the next frame
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| 01:56 | Bertl | the task is to create a deserializer which can do 8, 10 and 12 bit not just 8 bit
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| 01:56 | Bertl | and you definitely do not want to drop any data
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| 01:57 | aSobhy | as generic module that can be set to the three sizes ?
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| 01:57 | Bertl | nope, at runtime
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| 01:58 | Bertl | to give you an idea, if the task were to handle 4 and 8 bit
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| 01:59 | Bertl | you could just do 8bit and provide a mechanism which can clock out 4 bit at twice the datarate
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| 01:59 | Bertl | or deserialize 4 bit and accumulate two 4 bit values to provide the 8bit output
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| 02:02 | aSobhy | ok
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| 02:04 | aSobhy | but for that case if i deserialize 4-bit i will out it on the main bus or the max bus i have (that is 8-bit ) and the rest of the bits is a don't care
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| 02:04 | Bertl | precisely
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| 02:04 | aSobhy | out them*
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| 02:05 | Bertl | the parallel output is always the highest bit depth
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| 02:05 | Bertl | i.e. 8bit in the 4/8 example and 12bit in the task
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| 02:05 | aSobhy | yes yes for sure
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| 02:06 | Bertl | the 'unused' bits (can be LSBs or MSBs) should be constant
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| 02:06 | aSobhy | yeah it will be fixed for all :)
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| 02:07 | aSobhy | now its clear :)
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| 02:07 | Bertl | great!
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| 02:07 | aSobhy | thank Bertl :D
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| 02:07 | Bertl | you're welcome!
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| 02:07 | aSobhy | thanks**
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| 04:29 | Bertl | off to bed now ... have a good one everyone!
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| 04:29 | Bertl | changed nick to: Bertl_zZ
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| 10:22 | se6astian | good
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| 10:22 | se6astian | day
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| 12:48 | Bertl | morning folks!
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| 12:54 | vup2 | morning
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| 14:11 | Topic | apertus° - open source cinema | www.apertus.org | join the apertus° Lab: http://lab.apertus.org/ | IRC Logs available at: http://irc.apertus.org
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| 14:11 | se6astian | has set the topic |
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| 18:44 | BAndiT1983 | vup2, anuejn: have removed input/output parameters from systemd service file, now the output is sent through std::clog either to terminal or if axiom_daemon is running as service to journal
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| 18:45 | BAndiT1983 | have still to check how to avoid sudo
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| 20:07 | vup2 | BAndiT1983: awesome
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| 20:08 | vup2 | Does that mean it doesn't use systemd anymore at all?
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| 20:08 | BAndiT1983 | yes, removed it a couple of days ago, will upload soon
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| 20:08 | vup2 | Is the socket handling still done by systemd?
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| 20:09 | BAndiT1983 | nope, have also not used it much before, as it always initialized "legacy" one
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| 20:09 | vup2 | Awesome
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| 20:10 | BAndiT1983 | what's the state with "void"? any news?
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| 20:29 | anuejn | qemu emulation works; untested on real hardware
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| 20:29 | anuejn | but will do that soon
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| 20:29 | BAndiT1983 | sounds good
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| 21:21 | BAndiT1983 | pushed new update and merged to master, circle ci is a bit picky today, it recognized dev branch as version 1.0 and refused to show it in the lsit, although we used 2.0 from the beginning on
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| 21:22 | BAndiT1983 | will email to Francis to ask him about his current progress, in the meantime CLI will be my main focus
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| 21:29 | se6astian | great
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| 21:30 | BAndiT1983 | off for today, good night
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| 21:33 | vup2 | sounds great
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| 21:34 | Kjetil | kkk
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| 21:34 | Kjetil | sorry
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| 21:34 | Bertl | yyy
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| 21:35 | Kjetil | One day I shall find my rj45 tool and fix the connector on this cable.
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| 22:20 | se6astian | off to bed
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| 22:20 | se6astian | good night
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| 23:15 | apurvanandan[m] | Does using existing hardened SERDES means using some IP core for it or something like that?
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| 23:47 | Bertl | apurvanandan[m]: no, but you can use the primitives
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