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| 05:31 | Bertl_oO | mithro: yeah, I know :)
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| 16:40 | manas | Bertl_oO: Kjetil: Sorry to disturb you again. I remade the i2c slave code . I started from scratch and included the spike suppressor and did the post implementation as well.
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| 16:40 | manas | The link to the code is here: https://github.com/Manas173/PWM-generator-and-I2C_slave/blob/master/i2c_slave_pwm_control.vhd
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| 16:40 | manas | I also uploaded the screenshot of post implementation simulation and the simulation source code in the same repository. Please let me know if its good enough.
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| 16:43 | Bertl_oO | looks a lot better at least from the readability, still some issues with indentation
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| 16:44 | Bertl_oO | I'm not sure it is a good sign that this is still an issue
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| 16:45 | Bertl_oO | anyway, please walk me through the i2c slave code ...
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| 16:46 | manas | Sorry for the indentation part.
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| 16:48 | manas | The i2c slave code is made using FSM where the start signal moves the state from idle to read_address
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| 16:48 | manas | Where it reads 7 bit address and sends an ack to the main entity through ack_addr
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| 16:49 | manas | The slave always read from the master and once the ack of address is complete, it moves to read the data part
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| 16:50 | manas | Here the data is 8 bit but can be altered in generic like to 16 bit.etc
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| 16:51 | manas | Once data is fetched ack is sent through the ack_data to the main entity
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| 16:52 | manas | After reading , the 8 bit data is sent to the pwm_generator
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| 16:54 | manas | The master has then the choice to wait or send 8 bit data or stop data transmission
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| 16:55 | manas | if data is sent the state goes back to receive data
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| 16:56 | manas | if stop bit is sent then state goes back to the idle and pwm generation is stopped
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| 16:57 | manas | The main entity includes spike suppression code to suppress spikes of maximum 60ns width
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| 17:00 | manas | There are four component instance of i2c slave having different address. The one whose address matches sends the data.
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| 17:01 | manas | Thats all.
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| 17:02 | Bertl_oO | okay, there are some parts which I do not like in the code ... honestly I'm surprised that your post implementation was successful
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| 17:03 | Bertl_oO | having checks for rising_edge() and falling_edge() on the same signal in the same process usually doesn't produce a working design
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| 17:04 | Bertl_oO | the problem here is that FFs cannot trigger on both edges and thus the tools usually simply ignore one condition
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| 17:04 | Bertl_oO | (might still be the case here and it 'just works' by accident)
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| 17:06 | manas | For the same clock signal both the edges worked on the same signal and there were no warning or issues. If the triggering is still the problem, please give some time I will try to fix this issue.
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| 17:07 | manas | Just wondering if I can proceed discussion on a project or fix this issue first considering limited time
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| 17:08 | Bertl_oO | try the following simple example with your tools and simulation:
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| 17:08 | Bertl_oO | https://pastebin.com/raw/ercnENTU
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| 17:09 | mithro | You got into GSoC again!
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| 17:09 | mithro | Yay \o/
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| 17:09 | Bertl_oO | did we? great!
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| 17:10 | manas | Congats
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| 17:12 | Bertl_oO | tx
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| 17:22 | davidak[m] | \o/
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| 17:37 | manas_ | Bertl_oO : The simulation is not working as expected the out is not triggered by clk
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| 17:37 | Kjetil | That's because Bertl_oOs code is evil
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| 17:37 | Kjetil | But a good example non the less
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| 17:37 | Bertl_oO | manas_: did you get any warnings or errors?
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| 17:39 | manas_ | Yes that the register is unused and removed
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| 17:39 | Bertl_oO | so no specific warning about this 'evil' code then ...
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| 17:40 | Bertl_oO | the problem here is that this kind of code makes VHDL developer very uneasy ... which also applies to the rising/falling mix in your code
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| 17:41 | Bertl_oO | i.e. you probably have to explain _why_ it works as intended in this specific case (if it does) because in general this kind of coding results in non-functional or at least misbehaving implementations
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| 17:42 | Bertl_oO | and even then, it still leaves a bad aftertaste because it can break every moment when you change the tools or maybe even use a different FPGA
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| 17:43 | Bertl_oO | in general, don't do it ... especially as I do not see any need for that in an I2C slave :)
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| 17:44 | Bertl_oO | that said, you can consider the qualification task completed, but the quality will be judged as well when we come to the point where we select the students
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| 17:45 | manas_ | Thank you so much I will make it upto the mark.
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| 17:45 | Bertl_oO | also note that there is still quite some time till we have to pick the students
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| 17:45 | supragya | hi
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| 17:45 | Bertl_oO | hey supragya!
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| 17:45 | supragya | hi Bertl_oO, I have looked over the PHABICATOR link just now, i am interested in GSoC 2018
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| 17:46 | supragya | "Live histogram, waveform, vectorscope" - this interests me
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| 17:46 | manas_ | Bertl_oO: I will contact you soon enough for the project discussion. Thanks again
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| 17:46 | Bertl_oO | you're welcome!
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| 17:46 | Bertl_oO | supragya: sounds good!
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| 17:46 | supragya | I have looked over the code of cmv_hist3 given there
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| 17:47 | supragya | However, there are some trivial questions i would like to ask
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| 17:47 | Bertl_oO | go ahead
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| 17:48 | supragya | is this code for a different kind of camera... AXIOM if i am not wrong
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| 17:48 | supragya | so, if i am not wrong...
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| 17:49 | supragya | what you expect is live histogram, waveform, vectorscope in firmware (if i can call that)
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| 17:49 | Bertl_oO | hmm, not sure what your question is ... the AXIOM Beta is the camera
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| 17:49 | supragya | with supposedly crop feature
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| 17:50 | supragya | yeah... so if i would like to tinker around with cmv_hist3 code,
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| 17:50 | supragya | how can i emulate that on my end and see it working...?
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| 17:51 | Bertl_oO | that is a good question, but luckily rather simple to answer ...
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| 17:52 | Bertl_oO | the architecture on the AXIOM Beta is ARM, so you can either find a piece of ARM based hardware (like a Raspberry Pi) or use QEMU to emulate an ARM based system
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| 17:53 | Bertl_oO | the FPGA burst the image data into memory, so the raw images 'just' show up somewhere in RAM
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| 17:53 | Bertl_oO | (this can be easily simulated with the mimg tool)
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| 17:53 | supragya | is it buffered, sliced or full raw at a time while access?
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| 17:53 | supragya | the image?
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| 17:54 | supragya | 'just' shows up... as in sliced or full at a time...
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| 17:54 | Bertl_oO | it is bayered raw data in a buffer
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| 17:55 | Bertl_oO | so you can do random access on it, although it is adviseable to optimize access to reduce the required memory bandwidth (and speed up performance)
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| 17:55 | supragya | just like expected in T872?
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| 17:55 | Bertl_oO | very similar yes
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| 17:56 | supragya | where can i know of the 'saving' layout in memory for the bayered raw data in RAM?
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| 17:56 | Bertl_oO | the data in the raw12 is 'packed' while the buffer uses a spread out version
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| 17:57 | supragya | i would like to know of access patterns in general... if you could guide me in that direction
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| 17:57 | Bertl_oO | check the mimg.c code for a general idea and maybe document it somewhere ...
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| 17:57 | Bertl_oO | if there are questions, do not hesitate to ask here
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| 17:58 | supragya | the data in the raw12 is 'packed' while the buffer uses a spread out version - these are both accessable and two different things? However i guess it would be more meaningful to ask this after going through 'mimg.c' i guess.
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| 17:59 | Bertl_oO | currently the memory layout is a combination of raw data and overlay
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| 17:59 | supragya | Can you tell me how and when should i complete T872 and submit and then continue with idea perhaps.?
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| 18:00 | Bertl_oO | well, we will use the qualification tasks to select the students
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| 18:00 | supragya | maybe document it somewhere - Did not quite get this, do you mean to find a documentation or write one myself for others to reference?
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| 18:00 | Bertl_oO | so they need to be complete when you finish your submission
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| 18:00 | supragya | qualification tasks - these are part of applications or prior to applications
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| 18:01 | Bertl_oO | yes, what I meant is that you should document things which are not well documented or not documented at all
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| 18:01 | Bertl_oO | this way you get a good understanding and the project benefits as well
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| 18:02 | Bertl_oO | in general I would suggest to complete the qualification tasks as soon as possible, just to get some feedback on the quality, etc
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| 18:02 | Bertl_oO | but technically it's enough to have them for the final application submission
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| 18:03 | supragya | ... sure... thank you for the time, I would like to get back with results soon. P.S. congratulations to the organisation to be a part of GSoC 2018.
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| 18:03 | Bertl_oO | thanks and have fun!
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| 18:03 | supragya | and Hrithik... hi. nice to have people onboard for gsoc too
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| 18:05 | supragya | in the idea page, it is expected to do T871 or T872. Is it okay to skip T871, or will it carry extra weightage incase both are done?
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| 18:08 | Bertl_oO | are you asking about T727?
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| 18:09 | Bertl_oO | in general, a well done qualification task should be more than enough, only when we will have a tie a second or third task will carry weight
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| 18:09 | supragya | T734
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| 18:10 | Bertl_oO | okay, not sure what you are referring to with the 'idea page'
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| 18:10 | supragya | sorry for being not precise
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| 18:11 | supragya | the page on "Live histogram, waveform, vectorscope" - T734
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| 18:11 | supragya | This page I am talking about : https://lab.apertus.org/T734
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| 18:11 | Bertl_oO | okay, so yes, pick one qualification task, solve it well and you should be fine
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| 18:12 | Bertl_oO | if you have spare time and want to make extra sure, do the other one as well
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| 18:12 | Bertl_oO | but keep in mind, quality over quantity
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| 18:12 | supragya | sure :)
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| 18:12 | supragya | TY
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| 18:12 | Bertl_oO | np
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| 19:26 | BAndiT1983 | Bertl_oO, you there?
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