#apertus IRC Channel Logs

The link to the code is here: https://github.com/Manas173/PWM-generator-and-I2C_slave/blob/master/i2c_slave_pwm_control.vhd

looks a lot better at least from the readability, still some issues with indentation

anyway, please walk me through the i2c slave code ...

The i2c slave code is made using FSM where the start signal moves the state from idle to read_address

The slave always read from the master and once the ack of address is complete, it moves to read the data part

Once data is fetched ack is sent through the ack_data to the main entity

The master has then the choice to wait or send 8 bit data or stop data transmission

if stop bit is sent then state goes back to the idle and pwm generation is stopped

There are four component instance of i2c slave having different address. The one whose address matches sends the data.

okay, there are some parts which I do not like in the code ... honestly I'm surprised that your post implementation was successful

the problem here is that FFs cannot trigger on both edges and thus the tools usually simply ignore one condition

For the same clock signal both the edges worked on the same signal and there were no warning or issues. If the triggering is still the problem, please give some time I will try to fix this issue.

try the following simple example with your tools and simulation:

You got into GSoC again!

did we? great!

tx

\o/

That's because Bertl_oOs code is evil

manas_: did you get any warnings or errors?

so no specific warning about this 'evil' code then ...

i.e. you probably have to explain _why_ it works as intended in this specific case (if it does) because in general this kind of coding results in non-functional or at least misbehaving implementations

in general, don't do it ... especially as I do not see any need for that in an I2C slave :)

also note that there is still quite some time till we have to pick the students

hey supragya!

"Live histogram, waveform, vectorscope" - this interests me

you're welcome!

supragya: sounds good!

However, there are some trivial questions i would like to ask

is this code for a different kind of camera... AXIOM if i am not wrong

what you expect is live histogram, waveform, vectorscope in firmware (if i can call that)

with supposedly crop feature

how can i emulate that on my end and see it working...?

the architecture on the AXIOM Beta is ARM, so you can either find a piece of ARM based hardware (like a Raspberry Pi) or use QEMU to emulate an ARM based system

(this can be easily simulated with the mimg tool)

the image?

it is bayered raw data in a buffer

just like expected in T872?

where can i know of the 'saving' layout in memory for the bayered raw data in RAM?

i would like to know of access patterns in general... if you could guide me in that direction

check the mimg.c code for a general idea and maybe document it somewhere ...

the data in the raw12 is 'packed' while the buffer uses a spread out version - these are both accessable and two different things? However i guess it would be more meaningful to ask this after going through 'mimg.c' i guess.

Can you tell me how and when should i complete T872 and submit and then continue with idea perhaps.?

maybe document it somewhere - Did not quite get this, do you mean to find a documentation or write one myself for others to reference?

qualification tasks - these are part of applications or prior to applications

this way you get a good understanding and the project benefits as well

but technically it's enough to have them for the final application submission

thanks and have fun!

are you asking about T727?

T734

sorry for being not precise

This page I am talking about : https://lab.apertus.org/T734

if you have spare time and want to make extra sure, do the other one as well

sure :)

np