| 01:21 | fredy | left the channel |
| 01:42 | tpw_rules | vup: anuejn: latest PR https://github.com/apertus-open-source-cinema/naps/pull/28
|
| 01:42 | tpw_rules | i discovered two things: the packet usually gets read from main RAM by dd at 4-6MB/s, but sometimes for no reason it's 70. can it be 70 all the time? is there something in the bus logic?
|
| 01:43 | tpw_rules | the other: PR #24 made the stream writer pass timing yes, but it also broke it and parts of the stream get dropped. if i revert the changes then it does not pass timing but works properly. can you investigate and fix?
|
| 01:43 | tpw_rules | also the third: did we come up with a good way to expose the HDMI output?
|
| 03:42 | Bertl_oO | off to bed now .... have a good one everyone!
|
| 03:43 | Bertl_oO | changed nick to: Bertl_zZ
|
| 06:50 | fredy | joined the channel |
| 11:19 | Bertl_zZ | changed nick to: Bertl
|
| 11:19 | Bertl | morning folks!
|
| 11:25 | anuejn | tpw_rules: nice
|
| 11:25 | anuejn | varying ram speed seems really wired
|
| 11:25 | anuejn | do you know if it has something to do with the ram reads / writes from the fpga side?
|
| 11:25 | anuejn | ouch #24 breaking it seems bad
|
| 11:26 | anuejn | re HDMI I think there is no good way for me to expose it but Bertl said that he will have a working camera soon
|
| 11:26 | anuejn | and his remote setup supports hdmi
|
| 11:53 | LordVan | joined the channel |
| 12:18 | vup | tpw_rules: the read speed is probably due to the sdcard?
|
| 12:19 | vup | 4-6MB/s seems like a reasonable speed for a normal sdcard
|
| 12:19 | vup | and the 70MB/s might be, when the kernel caches it for a bit before syncing
|
| 13:39 | LordVan | left the channel |
| 13:55 | Bertl | off for now ... bbl
|
| 13:55 | Bertl | changed nick to: Bertl_oO
|
| 17:22 | Spirit532 | left the channel |
| 17:22 | Spirit532 | joined the channel |
| 17:27 | fredy | left the channel |
| 19:00 | tpw_rules | vup: you were right, receiving to /dev/null is >300MB/s. i thought i tested that, but i guess i made a mistake
|
| 20:29 | tpw_rules | i fixed the DRAM writer by adding a StreamBuffer on the data stream. not entirely sure why that is necessary. and unfortunately that stops it from passing timing again...
|
| 20:38 | tpw_rules | it seems all the timing issues are input_dram_packet_ringbuffer_stream_writer/writer/burster/address_burster/last_address[N]
|
| 21:13 | fredy | joined the channel |
| 22:43 | fredy | left the channel |