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#apertus IRC Channel Logs

2019/06/11

Timezone: UTC


00:11
Spirit532
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00:40
Bertl
off to bed now ... have a good one everyone!
00:40
Bertl
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BAndiT1983
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09:09
Bertl_zZ
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09:09
Bertl
morning folks!
09:10
se6astian
good day
11:16
Bertl
off for now ... bbl
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Bertl
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BAndiT1983|away
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BAndiT1983
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BAndiT1983|away
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Y_G
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16:59
Bertl_oO
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16:59
Bertl
evening folks!
17:00
aSobhy
evening Bertl :)
17:01
Bertl
IIRC, you are going to tell us about JTAG today?
17:02
aSobhy
yes
17:02
Bertl
then please go ahead when you're ready
17:03
aSobhy
ok
17:03
aSobhy
apurvanandan[m]: are you here ?
17:05
aSobhy
Hi all, today I'll talk about jtag protocol
17:05
apurvanandan[m]
Yes, sorry for delay
17:07
aSobhy
first of all JTAG (Joint Test Action Group) is a serial protocol that is used for verifying designs and testing printed circuit boards after manufacture
17:08
Bertl
and programming devices in-circuit
17:10
aSobhy
we can use JTAG for:
17:10
aSobhy
1- Debugging
17:10
aSobhy
2- programming devices
17:10
aSobhy
3- Boundary scan testing
17:10
aSobhy
first Debugging :
17:14
aSobhy
we can debug what is the state of our component with a software to get what values for example BTS (Branch Trace Storage), LBR (Last Branch Record)
17:16
Bertl
okay, but that needs specific support on the device ... please try to keep it more general
17:17
Bertl
(maybe explain how JTAG communication works first and then let's look at use cases
17:17
Bertl
)
17:17
se6astian|away
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17:23
aSobhy
2- programming devices :
17:23
aSobhy
we can program our device using JTAG to write on the SRAM or Flash
17:23
aSobhy
do you mean start with the interface and TAP ?
17:23
Bertl
yes, let's start with that
17:23
aSobhy
ok
17:25
aSobhy
the JTAG has 5 pins interface:
17:25
aSobhy
1- TDI (Test Data In)
17:25
aSobhy
2- TDO (Test Data Out)
17:25
aSobhy
3- TCK (Test Clock)
17:25
aSobhy
4- TMS (Test Mode Select)
17:25
aSobhy
5- TRST (Test Reset) optional.
17:26
aSobhy
we can not use the TSRT as we will see next
17:32
aSobhy
first we have a Boundary Scan Register : which is the boundary I/O of the device it has an input of TCK and TDI
17:34
aSobhy
we can assign the values of the I/O pins in order to test our design or the program on the board
17:34
Bertl
are you reading the documentation right now or why does it take 5 minutes for each line?
17:37
aSobhy
no i didn't reharse sorry !
17:37
Bertl
okay, then try to get to the point: how does it work?
17:38
aSobhy
here what i'm talking from:
17:38
aSobhy
https://drive.google.com/open?id=1YQ0LVwgS4l2KPW4uC0lg30JlmxRYJTqm
17:39
Bertl
okay, so looking at this diagram, what can we do here?
17:39
aSobhy
we can assign the values of the Data Registers or the instruction register
17:40
Bertl
good, how do we do that?
17:40
aSobhy
and all of that can be controlled from the TAP controller
17:41
Bertl
how?
17:43
aSobhy
by the TAP controller https://drive.google.com/open?id=1Y6KUE6lEKvvoW-lMaFoxQ5keriEEzD0e
17:43
Bertl
so the tap controller controls the tap controller?
17:45
aSobhy
no !
17:46
aSobhy
its a sequence of states that we can assign from the TMS so we can shift for ex. the data register
17:47
Bertl
how do we 'assign' this sequence?
17:49
Bertl
can anybody help aSobhy out with the basics of JTAG?
17:50
aSobhy
our program we want to shift a new value in the register then we will send 0100(looping till all registers are done )
17:50
aSobhy
looping=0
17:55
aSobhy
!
17:56
Bertl
now everything is clear ...
17:57
aSobhy
what is missing ?
17:58
Bertl
I doubt that anybody can understand JTAG from this description
17:58
Bertl
but let me help you get on track here
17:59
Bertl
as you mentioned, there are four central signals involved
17:59
Bertl
TMS, TCK, TDI and TDO
18:00
Bertl
TCK is the clock for serial data and on every clock cycle, data is shifted in from TMS and TDI and shifted out via TDO
18:00
Bertl
the data shifted in via TMS controls the TAP (controller)
18:01
Bertl
i.e. every bit on TMS decides in the JTAG TAP state engine what the next step is going to be
18:01
Bertl
(see diagram about JTAG TAP state engine :)
18:02
Bertl
there are several shift registers of certain length in a JTAG device
18:02
Bertl
the main registers are the command register and the data register
18:03
Bertl
ly one clock cycle delay
18:03
Bertl
there is also a short bypass register which allows to pass through any input data to the output with on
18:03
Bertl
(switch the last two lines :)
18:04
Bertl
which register is connected between TDI and TDO is controlled by the state of the tap controller and the command in the command register
18:04
Y_G
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18:05
Bertl
now let's pick up from here and explain some of the commands please ...
18:06
Y_G
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18:09
aSobhy
what commands ?
18:09
aSobhy
do you mean the state machine ?
18:10
Bertl
you can explain the state machine if you like to
18:10
Bertl
but I was more referring to the commands in the instruction register
18:15
aSobhy
no I didn't reach the Instruction register illustration but i saw it has it has
18:15
aSobhy
SAMPLE
18:15
aSobhy
EXTEST
18:15
aSobhy
PRELOAD
18:15
BAndiT1983
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18:16
aSobhy
SAMPLE : reading pin values into the boundary scan register
18:17
aSobhy
EXTEST : for external testing, such as using pins to probe board-level behaviors
18:17
aSobhy
PRELOAD : loading pin output values before EXTEST (sometimes combined with SAMPLE)
18:18
Bertl
any other important instructions?
18:19
aSobhy
BYPASS and IDCODE
18:19
Bertl
yup, what do they do?
18:23
aSobhy
BYPASS : an opcode of all ones regardless of the TAP's instruction register size, must be supported by all TAPs. The instruction selects a single bit data register (also called BYPASS). The instruction allows this device to be bypassed (do nothing) while other devices in the scan path are exercised
18:24
Y_|G
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18:24
Bertl
okay, how can this be used for device discovery?
18:24
Y_G
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18:26
aSobhy
no I don't know
18:28
Bertl
so the devices can be put in a so called chain
18:28
Bertl
where TDO of one device is connected to TDI of the next device
18:28
Bertl
and so on, till the loop is complete, having only one TDI and TDO on the jtag header
18:29
Bertl
TCK and TMS is routed to each of the devices in the JTAG chain
18:29
Kjetil
How would you know the amount of devices in the chain?
18:29
Bertl
by sending a long sequence of zeros/ones one can calculate the length of the instruction and data registers
18:30
Kjetil
:)
18:30
Bertl
and with IDCODE, it is possible to figure out what device is connected
18:32
Bertl
note that JTAG discovery can be quite complex
18:33
Bertl
aSobhy: okay, so I'm not really happy with the JTAG presentation, but you probably figured that from my comments ...
18:33
Bertl
let's move on and discuss the next steps ...
18:34
Bertl
apurvanandan[m] managed to program the MachXO2 on the plugin module yesterday
18:34
Bertl
you both managed to work with the MachXO2s on the Main Board last week
18:35
Bertl
so I expect the coming days to see some test code for the MachXO2s regarding data transfer
18:36
aSobhy
I feel sorry I can repeat it next week ?
18:36
Bertl
sure
18:38
Bertl
so any problems, questions, etc?
18:38
aSobhy
I want to talk about the protocol ?!
18:38
Bertl
okay
18:39
apurvanandan[m]
Bertl you said to do one more session on remote beta ?
18:39
aSobhy
what are the instruction will be sent and what I remember it will be a fixed length for every packet
18:40
apurvanandan[m]
When can we arrange that
18:40
aSobhy
instructions*
18:40
Bertl
well, we haven't decided that yet, as it depends on the performance we can achieve over the available connections
18:41
Bertl
apurvanandan[m]: yes, we can do that in the next few days, remind me what the focus is/was?
18:41
Y_|G
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18:42
Bertl
aSobhy: ideally we have low latency for GPIO data and high bandwdith for everything else
18:42
Bertl
we might need to do some scheduling to avoid timeouts etc
18:43
apurvanandan[m]
Ok
18:43
Bertl
and in general the packets will probably be of moderate size mainly because there isn't that much data to transfer and we want to keep low latencies for important stuff
18:44
Bertl
fixed length is fine for me, but if variable length gives us significant advantages, I wouldn't rule it out yet
18:45
Bertl
as planned, first step should be to evaluate what the communication channel can do in the Beta
18:46
Bertl
bonus points here for creative ideas to keep the overhead (mainly power consumption and noise) low when the channel is idle
18:50
aSobhy
I have a problem didn't understand
18:50
aSobhy
how I'll manage the devices with different clocks ?
18:50
aSobhy
slow clocks
18:51
aSobhy
for the protocols (GPIO, I2C,...)
18:53
Bertl
well, clock need to be generated locally (they can be based on a common high speed clock of course)
18:54
Bertl
so if there is an I2C master (in the FPGA) it needs to provide a 'configured' clock to access the devices
18:55
Bertl
and if, on the other hand, the FPGA provides a slave/bridge interface, a clock domain crossing mechanism (e.g. FIFO) is required
18:55
Bertl
but in the current setup we all assume master functionality on the FPGA side
18:56
Bertl
so this problem should not be relevant
18:58
aSobhy
okay
18:59
aSobhy
thanks Bertl
18:59
Bertl
you're welcome!
18:59
aSobhy
and sorry of what happened today :(
19:00
Bertl
okay
19:13
BAndiT1983|away
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19:26
Bertl
off for now ... bbl
19:26
Bertl
changed nick to: Bertl_oO
21:08
BAndiT1983
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21:21
se6astian
off to bed
21:21
se6astian
good night
21:21
Bertl_oO
nn
21:22
se6astian
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