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#apertus IRC Channel Logs

2018/05/11

Timezone: UTC


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seaman
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Bertl_oO
off to bed now ... have a good one everyone!
02:12
Bertl_oO
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04:28
ymc98
supragya : Do you what are all the types of data is sent from zynq to the lattice boards? I have read the logs and all there is that I could find is RAW12. Please tell me the other data formats and the respective data rates.
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Bertl_zZ
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07:36
Bertl
morning folks!
07:37
Bertl
ymc98: raw12 data is very unlikely to be sent from the Zynq to the MachXO2
07:38
Bertl
the MachXO2s are routing fabrics for 'low speed' and 'low bandwidth' data like GPIOs, I2C and SPI bus systems
07:38
ymc98
I see
07:38
Bertl
the high speed interface (image data) is directly interfaced by the Zynq
07:39
Bertl
look at the main board schematic to get an idea what kind of data can be expected
07:40
ymc98
Will do
07:41
Bertl
http://vserver.13thfloor.at/Stuff/AXIOM/BETA/axiom_beta_main_board_v0.36_r1.2.sch.pdf
07:42
Bertl
page 5 and 6 show the MachXO2s
07:43
Bertl
you can see the PCIE_N/S_IO*s which are the low speed GPIOs to the plugin modules
07:44
Bertl
you see the SH_**_IO* which are the low speed GPIOs to the shields
07:44
Bertl
and a number of *_SDA/*_SCL or *_SDI/SDO/SCK which are I2C or SPI busses
07:46
Bertl
there are also mixed connections to the center solder on area labeled C_**_E/C_**_W
07:46
Bertl
those work either as GPIO, I2C or SPI bus
07:46
Bertl
and finally there are some additional GPIOs like for the fan control and the beeper
07:48
Bertl
also check your private messages on IRC
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test123
please ignore me ...
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11:45
vup
Bertl: do you know where we can find the gateware of the sdi module?
11:47
Bertl
you have to check with felix_ or _florent_
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Bertl
off for now ... bbl
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Bertl
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RexOrCine|away
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BAndiT1983|away
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sebix
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14:32
felix_
vup: the final gateware for the sdi module isn't ready yet. i'm currently working on the hardware
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BAndiT1983
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BAndiT1983|away
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BAndiT1983
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17:12
Bertl_oO
felix_: I guess he was referring to the one used on the SDI prototype
17:13
felix_
ah
17:17
felix_
the gateware of the prototype still contained some proprietary parts (that was stil useful to test if the hardware of the first prototype works), but i'll definitely continue my work on the fully open source photonSDI gateware. getting the design for the final extension module ready is more time-critical at the moment though
18:42
vup
felix_: ahh, thanks for the clarification
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RexOrCine
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BAndiT1983|away
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RexOrCine|away
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22:11
RexOrCine
Pirl 4 Port 10 Amp USB Charger Teardown: https://youtu.be/pnCnFHNMpxE
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BAndiT1983
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23:16
Bertl_oO
off to bed now ... have a good one everyone!
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Bertl_oO
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