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#apertus IRC Channel Logs

2021/04/11

Timezone: UTC


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BAndiT1983
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pani
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03:52
pani
Hi anyone online?
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pani_
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BAndiT1983|away
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metal_dent[m]
pani: hello
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07:07
Bertl
off to bed now ... have a good one everyone!
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Bertl
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BAndiT1983
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09:32
lambamansha
how to set parameters of registers of axiom beta via axiom webUI ? (It will happen via nctrl , I could see file nctrlValue.js in webUI but can anyone give low level understanding of the same )
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pani_
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10:49
pani
Would the drafts be reviewed if challenge is not yet done. I intend to submit both proposal and challenge in final submission. But a review of draft would be helpful
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14:46
se6ast1an
hi pani, combined would be preferred but we can also review just one of them of course
14:46
pani
Ok good to know
14:46
se6ast1an
note that the closer we get to the deadline the more proposal reviews pile up so we might run out of time
14:47
pani
Yes I understand that ideally I would like to submit both at once. But I choose a hard idea to work on :-)
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manav
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14:54
se6ast1an
interesting :)
15:13
manav
for the eMMC Plugin Firmware project
15:14
manav
will the the lattice fpga act as a interface between the ZYNQ and emmc
15:15
manav
and will the fpga control the multiple EMMCs
15:16
manav
if yes, that means the software running on Zynq ps sees the lattice fpga as a emmc ?
15:24
BAndiT1983|away
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15:25
se6ast1an
hi manav
15:26
manav
Hi
15:26
se6ast1an
I am not the mentor of this task but my understanding is that the lattice fpga indeed acts as bridge or interface between zynq and the actualy flash memory
15:26
manav
ok thanks
15:26
se6ast1an
a single connected emmc would be the starting point I assume
15:27
se6ast1an
I do not think the zynq PS side is connected, its FPGA gateware only
15:28
se6ast1an
but Bertl_zZ should be awake soon
15:28
se6ast1an
and surely can clarify
15:31
Bertl_zZ
changed nick to: Bertl
15:31
Bertl
morning folks!
15:33
Bertl
hello manav
15:33
manav
hi
15:34
Bertl
the MachXO2 on the eMMC Plugin has a single eMMC to work with (currently) and is connected to the ZYNQ PL (fabric) side
15:35
Bertl
so it doesn't act as eMMC towards the ZYNQ, instead the ZYNQ and the eMMC plugin communicate via LVDS channels (up to six)
15:39
manav
ok.So,what exactly is the role of the lattice fpga?
15:40
Bertl
to handle the eMMC protocol stack and convert from the eMMC interface to the LVDS interface
15:41
Bertl
in a second step, the eMMC plugin will get more than one eMMC and then the plugin FPGA also has to distribute data between eMMCs
15:45
manav
So, the lattice FPGA will run 'eMMC host VHDL architecture' and communicate with eMMC via MMC protocol .. and receive commands and data from ZYNQ via LVDS link?
15:48
Bertl
that's it
15:50
manav
Noted, Do we also have to make LVDS based MMC host on ZYNQ PL or there is aleady some mechanism to communicate MMC commands from eMMC driver running on ZYNQ PS to these LVDS lines?
15:51
pani
Questions regarding the schematics
15:51
pani
1. The Zedboard has 48 LVDS pairs, all are not exposed on the PCB only the 4 to RFW and 2 to RFE?
15:51
pani
2. “It hosts two external medium-speed shield connectors and two high-speed plugin module slot connectors.” I am assuming that the PCIE connectors are the high speed and the X-West and X-East on schematic are the medium speed? Is this correct
15:51
pani
3. Zynq LVDS is not directly connected to Lattice FPGA, they are connected to the PCIe connector which is connected to the Lattice FPGA, the Lattice LVDS takes data from the plugin boards etc and sends input from the shields etc to the Zynq,is this understanding correct?
15:53
Bertl
1) we are using the MicroZed not the Zedboard and most of the LVDS pairs available there are used up for the sensor connection (35), the high speed plugin slots (6 each) and the East side shield (4)
15:54
Bertl
2) yes, the PCIe connectors are the high speed interfaces, they do not use PCIe protocol, we just used them because they are easily available and support high frequencies
15:55
Bertl
the 'Main Board' contains two Lattice MachXO2s which act as routing fabric / GPIO expander and handle all the medium/low speed stuff on plugins, shields and center solder on
15:56
Bertl
3) depends on what Lattice FPGA you are referring to :)
16:00
pani
I was assuming the question is relevant to both Lattice, RFW is having 1 pair and RFE is having 2
16:01
Bertl
okay, so you are talking about the Routing Fabrics (RFE and RFW)
16:02
Bertl
they are, as you correctly stated, connected with one or two LVDS pairs with the ZYNQ
16:02
Bertl
they also share a single ended clock line with the ZYNQ
16:03
markusengsner
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16:03
manav
Do we also have to make LVDS based MMC host on ZYNQ PL or there is aleady some mechanism to communicate MMC commands from eMMC driver running on ZYNQ PS to these LVDS lines?
16:05
Bertl
on the LVDS side, we do not plan to use MMC or related protocols, we basically want to send a stream of data through the LVDS lines and store the data on the eMMC(s)
16:06
Bertl
or the other way round, retrieve a stream of data from the eMMC(s) and send it over the LVDS pairs
16:06
Bertl
i.e. no MMC Host or Device involved there
16:07
manav
Noted
16:12
pani
So I am thinking of an example scenario, if the CSO board has some kind of sensor on it, the sensor data goes to one of the routing fabrics LVDS and from there goes the MiniZed through the Zynq LVDS which is connected to the routing fabric. Currently this data transmission is done by bitbanging instead of any gateware, so the aim of the potential Bidirectional FPGA communication project is bring up the PHY so that it is all the serial communication is handled
16:12
pani
by FPGA silicon without any software?
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16:54
Bertl
pani: yes, that's about what we want to do
16:56
Bertl
the RF gateware needs to be flexible enough to handle different protocols though, like I2C, SPI, JTAG, UART, GPIO, etc
16:57
Bertl
but the first step there is to get reliable FPGA-FPGA communication working
17:02
pani
Great that brings a lot of clarity
17:02
pani
Also just for clarification
17:02
pani
Implement the communication layer and add bit error rate as well as latency checks.
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17:03
pani
This communication layer is the layer above the physical layer in OSI model right? It is obvious I think but I want to confirm I understood it right
17:05
Bertl
yes, the physical layer (Of the OSI model) is the LVDS, the data link layer is the bidirectional protocol
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BAndiT1983
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