#apertus IRC Channel Logs

pani: hello

off to bed now ... have a good one everyone!

Would the drafts be reviewed if challenge is not yet done. I intend to submit both proposal and challenge in final submission. But a review of draft would be helpful

Ok good to know

Yes I understand that ideally I would like to submit both at once. But I choose a hard idea to work on :-)

interesting :)

will the the lattice fpga act as a interface between the ZYNQ and emmc

if yes, that means the software running on Zynq ps sees the lattice fpga as a emmc ?

hi manav

I am not the mentor of this task but my understanding is that the lattice fpga indeed acts as bridge or interface between zynq and the actualy flash memory

a single connected emmc would be the starting point I assume

but Bertl_zZ should be awake soon

hello manav

the MachXO2 on the eMMC Plugin has a single eMMC to work with (currently) and is connected to the ZYNQ PL (fabric) side

ok.So,what exactly is the role of the lattice fpga?

in a second step, the eMMC plugin will get more than one eMMC and then the plugin FPGA also has to distribute data between eMMCs

that's it

Questions regarding the schematics

2. “It hosts two external medium-speed shield connectors and two high-speed plugin module slot connectors.” I am assuming that the PCIE connectors are the high speed and the X-West and X-East on schematic are the medium speed? Is this correct

1) we are using the MicroZed not the Zedboard and most of the LVDS pairs available there are used up for the sensor connection (35), the high speed plugin slots (6 each) and the East side shield (4)

the 'Main Board' contains two Lattice MachXO2s which act as routing fabric / GPIO expander and handle all the medium/low speed stuff on plugins, shields and center solder on

I was assuming the question is relevant to both Lattice, RFW is having 1 pair and RFE is having 2

they are, as you correctly stated, connected with one or two LVDS pairs with the ZYNQ

on the LVDS side, we do not plan to use MMC or related protocols, we basically want to send a stream of data through the LVDS lines and store the data on the eMMC(s)

i.e. no MMC Host or Device involved there

So I am thinking of an example scenario, if the CSO board has some kind of sensor on it, the sensor data goes to one of the routing fabrics LVDS and from there goes the MiniZed through the Zynq LVDS which is connected to the routing fabric. Currently this data transmission is done by bitbanging instead of any gateware, so the aim of the potential Bidirectional FPGA communication project is bring up the PHY so that it is all the serial communication is handled

pani: yes, that's about what we want to do

but the first step there is to get reliable FPGA-FPGA communication working

Also just for clarification

yes, the physical layer (Of the OSI model) is the LVDS, the data link layer is the bidirectional protocol