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| 00:49 | Bertl | markian: well, basically the task is to 'convert' a bunch of high speed links (~1GHz) into 32bit 'moderate' speed parallel signals
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| 00:49 | Bertl | the challenge is to get the most out of the high speed links as well as the 32bit parallel port
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| 00:57 | apurvanandan[m] | Could you please provide the documentation of USB 3.0 plugin module https://github.com/apertus-open-source-cinema/apertus_multimedia/blob/master/Photos/AXIOM Beta USB 3.0 Plugin Module 01.png
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| 01:00 | Bertl | so on the HDL side, it will be at least two clock domains, encoding, serialization, deserialization, probably CRC, maybe (F)ECC, FIFOs and synchronization
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| 01:01 | Bertl | apurvanandan[m]: the only documentation available for the module so far is the schematic and layout (and of course all the available documentation from FTDI and Lattice)
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| 01:29 | apurvanandan[m] | is there any kind of criteria such as to have some number of pull requests in order to get accepted in the project?
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| 01:32 | Bertl | no you can work with us anytime ... for GSoC 2019, we will select those applicants which seem most promising for the tasks they applied for
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| 01:34 | Bertl | this includes but is not limited to coding style, creativity, self organization, communication and of course existing contributions
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| 01:48 | Bertl | off to bed now ... have a good one everyone!
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| 01:48 | Bertl | changed nick to: Bertl_zZ
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| 01:49 | apurvanandan[m] | I read your brochure where i found you already have completed 1080p HDMI plugin module. Could you please provide the gearwork/ HDLs for it?
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| 05:55 | aSobhy | hi, I'm new here :)
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| 05:55 | aSobhy | I'm asking in the vhdl challenge task1 : how I will get the n-bit encoded from the serialization to be decoded in the 12-bit format
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| 05:55 | aSobhy | are they encoded in the format of 3b/4b as ibm code so the output encoding will be 16-bit ? am I right ?
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| 08:07 | vup2 | apurvanandan[m]: it can be found here https://github.com/apertus-open-source-cinema/axiom-beta-firmware/tree/master/peripherals/soc_main
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| 08:13 | vup2 | aSobhy: i am not sure what you mean by ibm code, but task1 is only about deserialization, so you have a serial input of one bit and every 8 / 10 or 12 bits from this input form a output word
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| 09:48 | aSobhy_ | I thought I have to implement a clock recovery to determine the clock frequency of the serilaized words so the words are encoded for that reason and I have to decode them . But it seems eathier than what I thought . Is that right ?
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| 10:08 | vup2 | aSobhy: ah maybe i read the task wrong, best to ask Bertl_zZ when he wakes up
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| 10:17 | Bertl | morning folks!
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| 10:19 | Bertl | apurvanandan[m]: https://wiki.apertus.org/index.php/Beta_HDMI_Plugin_Module is the hardware and the HDL for this module is on the ZYNQ side
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| 10:22 | Bertl | you can find the HDL somewhere on https://github.com/apertus-open-source-cinema
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| 10:22 | Bertl | (lost track where it was moved last time :)
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| 10:22 | vup2 | morning
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| 10:23 | vup2 | re where it was moved: it says it right in the readme :)
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| 10:24 | Bertl | there is a readme?
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| 10:24 | vup2 | ah thought you had linked the axiom-beta-firmware repo
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| 10:25 | vup2 | (and not the whole github organization)
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| 10:25 | Bertl | aSobhy: for the challenge task, you do not need to do any clock recovery or decoding, for the first task we assume you have a clock which is at least related to the data
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| 10:27 | Bertl | apurvanandan[m]: so https://github.com/apertus-open-source-cinema/axiom-beta-firmware specifically https://github.com/apertus-open-source-cinema/axiom-beta-firmware/tree/master/peripherals/soc_main is where you should look
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| 10:28 | Bertl | rgb_hdmi.vhd is the data conversion and enc_*.vhd are the encoders (tmds, terc4 and ctrl)
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| 14:36 | aSobhy_ | Thanks Bertl :)
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| 14:46 | Bertl | you're welcome!
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| 14:47 | siddhantsahu | Would this feature of creating out own LUTs(2D and 3D) be helpful for OpenCine user?
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| 14:48 | siddhantsahu | https://3dlutcreator.com/
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| 14:52 | Bertl | check with BAndiT1983|away when he returns
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| 14:53 | siddhantsahu | Bertl: Ok
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