#apertus IRC Channel Logs

good morning

morning folks!

hey Francky

good good

unfotunately its raining today so we cannot film unloading the CNC mill...

https://wiki.apertus.org/index.php?title=Compact_CNC_Mill_Evaluation#Tormach

you plan to produce yourself the camera in production ?

but the main purpose is to have something for quick prototyping

did you find a compromise about all the board interfraces finally ?

I still have to check if we go for an iCE40 or maybe MachXO2

yeah, well, it's more digging through datasheets

on the wiki you said that the pl take images from sensor and store them into memory

so you use the external DDR memory, and the PL access to it throught AXI right ?

with something like a rouded buffer

the memory manager is a part of the PS ?

it is part of the zynq hardened peripherials

http://blog-imgs-51-origin.fc2.com/m/a/r/marsee101/Zynq_test_1_120715.png

thanks for the picture

you can run DMA (on the PS) to the DDR memory

ok so the chain is sensor -> PL -> AXI -> memory controller -> DDR

correct

right ?

thanks

when you say it is a frame buffer, do you mean that only the last video image is storen into memory ?

but the design allows arbitrary frame numbers (as long as you have enough memory)

correcy

and this IP just calculate the adress of the start of the frame or it need to calculate every adress of every pixel ? ie : is there burst mode (you give the start adress and the data in burst mode) ?

complicated calculations :)

i.e. the tools not always manage to get the routing right

correct

so you compile your project time after time as far as you get a correct routing ?

but I use your project with your tcl script, doesn't it integrate the "good" options ?

as I said, the tools are non-deterministic

I got rather annoyed by this fact at some point, and the many pblocks help to guide the tools somewhat, but it's not perfect

it is disturbing because you cannot garanty that the built program will have the same performance in each builder

afternoon Bertl, Francky :)

yeah, I have a bunch of ideas how to improve that for the Beta

designs = vhdl code or placement and routing of blocks ?

so you plan to make manually the job of the placer and router ?

I can understand that the tools have to make somewhat random decisions, because the search space for routing becomes very large with recent FPGAs

autorouter makes me ill

but in fact it is quite undestandable because it IS routing in fact

off for now ... bbl

I just visited the event location for the AXIOM kickoff

at the angewandte innovation lab, central vienna

can't wait!

se6astian: I re-added that photo. It disappeared. Was it a URL link?

but its fine that way as well now

what images could we add to spice up the second half?

instead of the result curves

did they show people color swatches?

seems they showed a white screen with two separated colors

we got sponsored by a flower delivery company

or chocolate

you know where to go now

thats what 100€ of camera development support gets you :)

well, that's big advertising I'd say ... after all the channel is logged :)

goood night