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#apertus IRC Channel Logs

2020/04/10

Timezone: UTC


01:29
Dest123
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02:08
Bertl_oO
off to bed now ... have a good one everyone!
02:08
Bertl_oO
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04:12
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06:46
BAndiT1983|away
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11:04
Bertl_zZ
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11:05
Bertl
morning folks!
11:11
se6ast1an
good day
11:23
BAndiT1983
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BAndiT1983|away
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13:10
comradekingu
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14:21
Dest123
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15:03
vup
Bertl: got some preliminary results with the connector test, for now without a connector, as we didn't have a soldering iron handy, but interesting nonetheless. The pins were just bridged with a resistor wire (held together by mechanical force).
15:03
vup
https://files.niemo.de/freq_max_success_res_wire.png
15:03
vup
https://files.niemo.de/freq_tap_res_wire.png
15:05
vup
this is using a differential pair (but the board layout wasn't made specifically for differential pairs, the traces are still quite close in their routing)
15:06
vup
and to count successes / errors currently a simple counter is transmitted, if last_received + 1 != current_received it is counted as an error
15:11
vup
(code is here: https://github.com/axiom-micro/nGateware/blob/axi/src/connector_test.py )
15:44
Bertl
indeed interesting ...
15:50
Bertl
if I interpret the dots correctly, at ~500 MHz you can transfer data without error at any tap setting?
15:50
vup
well 250MHz DDR
15:50
vup
but yes
15:51
vup
one thing to note is, that the delay refclock was connected to the output serdes clock
15:51
Bertl
why that?
15:51
vup
so at every frequency 32 delay taps should be half a clock period
15:52
Bertl
ah, I don't think the delay elements work this way :)
15:52
vup
(which with DDR means it should move over the complete range of one bit in 32 taps once)
15:52
Bertl
but it kind of explains the results
15:52
vup
Bertl: really, how do they work?
15:52
Bertl
they require a fixed frequency (narrow range) to drive a PLL
15:53
vup
well it says that
15:53
vup
but I think you actually have a bit more freedom
15:53
Bertl
IIRC, it's about 200-210MHz
15:53
Bertl
for the Zynq/Artix
15:54
Bertl
the high end 7series can go higher and thus create shorter delays
15:55
Dest123
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15:57
vup
hmm yeah maybe, however I think the results show that it seems to work for other frequencies aswell
15:57
Bertl
yes, but not sure what exactly works ... have to check the code (which I will do later)
16:00
vup
also there is xapp707 which has some interesting things about different refclock frequencies for idelayctrl (though for virtex-4 i think)
16:00
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16:03
omar31
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16:06
BAndiT1983
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16:08
Bertl
vup: do you get a ready signal from IDELAYCTRL at your frequencies (and do you check for it before testing)?
16:09
megora
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16:15
anuejn
Bertl: it is broken out as an axi reg so i could check
16:16
anuejn
For that sweep ti wasnt checked tho
16:17
vup
Should be easy to do some quick checks for the low frequencies tho
16:19
anuejn
Actually one of the diff pair ends was bridged with a pair of scissors
16:20
Bertl
medical scissors?
16:21
anuejn
nail scissors ;)
16:22
anuejn
so it is not the most scintific setup possible
16:25
anuejn
a quick test shows, that fclk_ready is high for 100Mhz 200Mhz and 250Mhz
16:25
anuejn
even for 50Mhz and 330Mhz
16:26
anuejn
with 5Mhz it is low
16:26
Bertl
fclk_ready?
16:26
Bertl
I'm talking about the ready signal from the DELAYCTRL
16:27
anuejn
idelay_crl_rdy
16:27
anuejn
thats what i meant
16:27
Bertl
okay
16:28
Bertl
RST was applied too I presume (on clock change)
16:30
anuejn
yes
16:31
Bertl
what really surprises me is that the documentation states that RDY will go low when REFCLK is high or low for more than one clock period
16:32
Bertl
so how does the IDELAYCTRL know that 50Mhz isn't 100MHz with 2 clock cycles high/low
16:32
anuejn
hm...
16:33
vup
Maybe it means that in the case of changing the frequency?
16:34
Bertl
yes, my understanding was that there is a narrow band PLL in the delay element
16:34
vup
If it has some internal pll it could know that it was low for x clock cycles of the previous clock
16:34
vup
Yeah
16:34
Bertl
well, not the delay element, the delay control element
16:34
Bertl
but that wouldn't work for 50-300MHz
16:35
Bertl
i.e. it would be way more likely that it generates 200MHz out of 100Mhz or even 50MHz
16:38
vup
So do you think it has a internal reference clock aswell?
16:38
vup
Or how does it know what the input frequency is?
16:38
Bertl
no idea
16:41
anuejn
i dont know a lot about that but i think the +-10% variation for the clock in the datasheet are realistic if they use an on silicon osc of some kind
16:42
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Dest123
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16:46
vup
well they specifically say they don't use one (atleast exclusively) because they use the external refclock to compensate for process / temperature / voltage variation
16:47
Bertl
as I said, my best guess would be a narrow band PLL
16:47
Bertl
but that doesn't match the results you got
16:47
Bertl
(i.e. PLL locking and delaying way out of specified range)
16:48
vup
yeah
16:49
vup
I guess one thing that we could try is looking at a fixed data frequency and then trying different idelayctrl refclock frequencies, that help clear something up
16:49
vup
s/that/that might/
16:50
Bertl
yep, good idea
16:55
vup
anuejn: wanna tried to that?
17:45
BAndiT1983|away
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18:11
anuejn
not now but generally yes :)
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19:29
Bertl
off for now ... bbl
19:29
Bertl
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BAndiT1983
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21:00
BAndiT1983|away
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