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| 07:49 | Bertl | morning folks!
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| 07:55 | cbohnens | good morning
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| 08:19 | Francky | hi all
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| 08:38 | Bertl | morning se6astian!
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| 08:46 | se6astian | good morning
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| 08:46 | se6astian | we are in the studio already :)
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| 08:47 | Bertl | great!
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| 12:19 | fadro | hi all
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| 12:20 | Bertl | hey fadro!
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| 12:24 | fadro | So quite on the irc today...
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| 12:25 | fadro | well let's make some noise with a small tips to discuss with.....
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| 12:26 | Bertl | hehe, go ahead!
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| 12:27 | fadro | Well coming from the IF board there will have a bunch of LVDS lanes to provide max video throuput (something like 50 lanes or wathever). But the trouble is that, since these lanes are affected to the video, they obviously cannot be affected to extending IO, so my question is the following:
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| 12:29 | fadro | Why not to allow some scalability on the IF video bus (let's call like this). For example, let's dedicate 40 lanes to the video, but provide 10 lanes which can be affected either to the video lanes or IO extension depending on the need.
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| 12:30 | fadro | because i imagiune that not all peoples will need the max throuput, so many lanes can be affected somewhere else...
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| 12:30 | Bertl | well, we have 36 LVDS pairs and a bunch of GPIO interfaces (SPI, I2C) on the interface board
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| 12:31 | fadro | Most of the LVDS pairs you are pseaking about are coming from both ICE 40 right?
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| 12:31 | Bertl | so the GPIO already cover most of the sensor low speed interfaces, what would be the purpose of dedicating high speed LVDS for I/O there?
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| 12:32 | Bertl | no, all LVDS pairs on the interface board come directly from the zynq
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| 12:32 | se6astian | another team talk in the can!
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| 12:32 | se6astian | not the trashcan :)
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| 12:32 | fadro | OK, sorry for the IF board.....don't read it, yes from the zynq, OK
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| 12:33 | Bertl | se6astian: opening another can of worms? :)
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| 12:40 | se6astian | changed nick to: se6astian|away
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| 12:51 | fadro | ok, just check the design, and concerning the IF board, i was speaking with the next IF board revision, the one with the FPGA.
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| 12:52 | fadro | So the idea on this new IF revision board was to allow a max sensor throuput, and this should be done by maximazing the IF bus size
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| 12:53 | Bertl | correct
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| 12:54 | fadro | OK, but i can imagine that some users will be interested in have a max sensor throuput while others won't
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| 12:54 | Bertl | most likely
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| 12:58 | fadro | so my thinking was to say : let's leave a part from this IF bus (so from the IF fpga to the µZ fpga) scalable, ie, having the choice to route some lines to the IF board if needed otherwise, reroute them to an extension IO connector (maybe plugin or shield?) to provide higher IO to external applications)
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| 13:00 | Bertl | the low power FPGAs have not the throughput the zynq has, so routing zynq LVDS pairs through them would significantly reduce the throughput
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| 13:00 | Bertl | ignoring that for a moment, the question is why would somebody who doesn't want full sensor bandwidth, require more I/O bandwidth?
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| 13:06 | fadro | if i Well the idea was not to use the LP fpga but a dedicated mux to achieve such operation. And getting the full BW form the sensor is great, but with the current design i see not enought IO BW (on shields or plugins) to exploit such dataflow, for example, i see no ways to put on a custom plugin board things like 6G SDI, or a SATA3 msata ssd because of the IO bottleneck (6 LVDS))
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| 13:07 | Bertl | you have 12 in total for a double plugin module, but I agree, it might be an option to reroute the now µC "dedicated" 6 LVDS channels there as well
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| 13:07 | Bertl | making a total of 18 LVDS pairs, which should be enough
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| 13:09 | Bertl | but it is probably a little tricky to get those pairs to the other side of the board
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| 13:12 | fadro | you mean tricky because of the 4 layers pcb constraints?
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| 13:12 | Bertl | yes
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| 13:14 | fadro | Well, why not to put an small Artix on the Beta rather than 2 ICE40. OK it will need a bit more power, but it will provide more flexibility and throuput.
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| 13:21 | Bertl | also a routing problem
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| 13:22 | Bertl | i.e. we would need to have it in the middle somewhere
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| 13:22 | Bertl | but you're welcome to try a design
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| 13:25 | fadro | well just having a quick look, i see no "easy to solder" packages in the Artix family. I guess this is also a constraint to take into account? Boards should be handed soldered?
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| 13:39 | Bertl | or at least reflow with the OSHpark constraints
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| 13:39 | Bertl | which unfortunately rules out most BGA packages
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| 13:44 | Bertl | but I was considering the MachXO2 instead of the iCE40 for the "medium speed" I/O routing
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| 13:44 | Bertl | which might be a little more powerful
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| 13:47 | Bertl | haven't got the time to do a comparison with pros/cons yet though
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| 13:50 | fadro | the MachX02 100 pins TQFP could be a nice candidate! But routability needed to be checked even with this one.
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| 13:51 | Francky | why do you limit the pcb ordering to OSHpark ?
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| 13:51 | Francky | which seems to have hard contraints
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| 13:52 | Bertl | because it allows folks all over the world to get cheap PCBs and make some modifications to the design
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| 13:52 | Bertl | they are reasonably good quality and are not produced under dubious conditions
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| 13:55 | Bertl | and the constraints are not that hard, if you consider that somebody should be able to assemble the boards at home or at a fab lab
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| 13:56 | Bertl | of course, as PCB designer, it is always better to have smaller features, more layers, etc :)
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| 14:09 | Francky | ok
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| 14:31 | se6astian | hi masplund
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| 14:41 | se6astian | hi masplund
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| 14:43 | Bertl | accept it, he doesn't want to hi you :)
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| 17:10 | Francky | bye
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| 17:14 | Bertl | cya
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| 17:19 | fadro | There something unclear to me on certains power distribution branchs:
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| 17:19 | fadro | for example, W_VW power line start from power board to the PWR-NW connector, goes into the beta board where it goes to XWest connector where it arrive to the IF board Xwest connector, where it is looped back to the power board through NW connector to finally reach the same power board starting point!
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| 17:21 | Bertl | yeah, that is kind of a legacy
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| 17:22 | Bertl | it is very likely that we will drop the Xwest connection once the power connector setup is verified
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| 17:23 | Bertl | for now, you can see it as two supply pathes for those power connections
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| 17:23 | Bertl | in an earlier version, we had the power supply handled via the X-WEST/EAST connectors
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| 17:24 | Bertl | but that was suboptimal, which is why we introduced the PWR-NW/SE connectors
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| 17:24 | Bertl | the W_VW and E_VE conenctions are a leftover
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| 17:25 | fadro | Yes, that's what i saw but didn't understand yet. So these 2 connectors pin will not be mounted at the end, right?
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| 17:26 | Bertl | actually it's six on each X connector
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| 17:27 | Bertl | and they will get freed up for other connections soon
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| 17:47 | aombk | is the beta "within schedule"?
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| 17:49 | Bertl | aombk: within what schedule? :)
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| 17:52 | aombk | i see... so it will be delayed?:P
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| 17:53 | aombk | i remember eta april 2015
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| 17:53 | Bertl | yeah, so the schedule we advertized during crowd funding
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| 17:54 | Bertl | well, we might make it with the Early Beta
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| 17:54 | Bertl | (this will be part of the next update video)
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| 17:55 | Bertl | but I think you need to be very brave to get one of those, unless you're a developer
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| 17:56 | Bertl | so I would say, for the typical user, it is probably better to wait a month or two
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| 17:56 | aombk | i have no idea what early beta is. i will wait for the video
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| 17:56 | Bertl | yes, please do so, it will be out tomorrow or the day after I guess
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| 18:02 | fadro | Well, i imagine that PWR_SW is also a legacy since signals are routed down to the sensor board, but not used yet.
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| 18:04 | Bertl | the sensor board is designed to be rotation symmetrical
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| 18:04 | Bertl | i.e. the sensor board can be rotated 180° and plugged into the very same interface board
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| 18:08 | fadro | was it a request from folks? what the purpose of such option?
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| 18:09 | Bertl | to some degree, but the original reason for that was that we wanted to rotate the MicroZed to get the connectors out of the way
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| 18:10 | Bertl | together with the fact that the design was already very symmetrical
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| 18:10 | Bertl | we decided that we can easily make that a feature
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| 21:51 | se6astian | time for bed
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| 21:51 | se6astian | good night
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