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#apertus IRC Channel Logs

2019/12/09

Timezone: UTC


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Bertl_oO
off to bed now ... have a good one everyone!
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Bertl_oO
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10:58
phiLCeee
Morning folks, how is it going?
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BAndiT1983|away
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BAndiT1983
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13:08
se6ast1an
hi phiLCeee, not bad :) and how are you?
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Bertl_zZ
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13:25
Bertl
morning folks!
13:25
se6ast1an
good day
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15:12
se6ast1an
new team talk episode is out!
15:12
se6ast1an
https://www.apertus.org/axiom-team-talk-15-2-gsoc-axiom-remote-article-december-2019
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16:54
anuejn
nice :)
16:58
BAndiT1983|away
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17:01
se6ast1an
weekly meeting time!
17:02
se6ast1an
anuejn: please go ahead!
17:02
anuejn
i was working on further development of the new shiny webui, that is to be used in connection with nctrl
17:03
se6ast1an
great, screenshot?
17:03
Bertl
(nobody knows about that yet)
17:03
anuejn
it now has a fancy landing page that shows a howto ssh connection and general explanation
17:03
anuejn
screenshot is https://files.niemo.de/Screenshot_2019-12-09%20AXIOM-web.png
17:04
anuejn
(as se6ast1an suggested)
17:04
anuejn
ah right Bertl
17:04
se6ast1an
good point, generral introduction woul make sense I guess
17:05
anuejn
vup and me started to build another attempt to build a hardware abstrtaction layer over all the peripherals of the camera
17:05
anuejn
it is called nctrl
17:05
anuejn
https://github.com/axiom-micro/nctrl/blob/master/Readme.md
17:06
anuejn
it can be used with the beta and the micro and is configured via yml files
17:06
anuejn
in connection with that we develop the webui i referred to
17:06
anuejn
https://github.com/axiom-micro/webui
17:07
anuejn
there is also code to integrate both projects with the existing firmware builds
17:07
anuejn
https://github.com/apertus-open-source-cinema/axiom-beta-firmware/pull/127
17:08
anuejn
there is also a build that can be tested :)
17:09
se6ast1an
most excellent
17:09
anuejn
we added further lua scripting, some infrastructure for describing constants and a better mock mode (to develop without a camera) to nctrl.
17:09
anuejn
i think thats it :)
17:09
se6ast1an
the test build is from 6 days ago, do you still recommend trying that one?
17:10
vup
note that lua scripting is being reworked at the moment, so the current api / look is not what it will be like after that
17:10
vup
se6ast1an: yes, i think that test build should still be fine
17:11
se6ast1an
great
17:11
anuejn
(it doesnt have the landing page yet)
17:11
se6ast1an
noted
17:11
se6ast1an
so quick updates from me:
17:11
se6ast1an
you saw the TT15.2 release today already
17:12
se6ast1an
next episode will be edited by max in january
17:12
se6ast1an
we ordered an all new compact enclosure set of cnc milled parts
17:13
se6ast1an
which will be assembled to a full V2 compact prototype
17:13
se6ast1an
I will now with the cnc parts done for now focus on the remote software again
17:14
se6ast1an
with BAndiT1983 and his bootloader and c++ efforts
17:14
se6ast1an
need to understand where we are now got get started
17:14
se6ast1an
got -> to
17:14
se6ast1an
thats it from me
17:14
se6ast1an
anyone else?
17:14
Bertl
well
17:15
Bertl
I've been further investigating the cam link 4k for our purpose
17:15
Bertl
and it looks like the device can be put into the default fx3 mode where firmware can be uploaded
17:16
se6ast1an
reference: https://wiki.apertus.org/index.php/Elgato_CAM_LINK_4K
17:16
Bertl
still unlcear is whether the FPGA has encryption enabled and/or is locked down, so that's something to figure out
17:17
Bertl
didn't do too much testing with the device for 'normal capturing' since I dismantled it for inspection and low level tetsting
17:18
Bertl
on the USB3 plugin side we now have a (hopefully working) test HDL code to emulate various write patterns and evaluate the throughput from the FPGA side
17:18
se6ast1an
the twitter post went softly viral with around 10.000 impressions: https://twitter.com/ApertusOSCinema/status/1202280446408773632
17:18
se6ast1an
https://twitter.com/GregDavill/status/1202498159093485568
17:18
se6ast1an
https://twitter.com/ktemkin/status/1203191350620909568
17:19
vup
btw, some other people seem to be investigating the cam link 4k aswell, this thread has some nice images without the chips: https://twitter.com/GregDavill/status/1203998610775371776
17:19
Bertl
yes, indeed
17:20
Bertl
any more cam link related infos/questions/etc?
17:21
se6ast1an
I think that topic is done
17:21
Bertl
so back to the USB3 plugin then :)
17:21
apurvanandan[m]
Did any one say USB3 :)
17:22
Bertl
this is implemented as a jtag configurable unit where you can set all the test parameters and read out performance counters
17:22
anuejn
what refers "this" to?
17:23
Bertl
the HDL code on the FPGA side
17:23
Bertl
(see previous sentence :)
17:24
Bertl
so it allows for modes where data is only transferred when the fifo is not full as well as generic write always (potentially with data loss) and does accounting based on the feedback from the FTDI
17:24
apurvanandan[m]
Is someone working on USB 3 plugin module?
17:24
Bertl
yes, obviously I am :)
17:25
Bertl
I've also started to write some bulk receive code using libusb and should shortly see whether this works or not (bypassing the proprietary FTDI library)
17:26
se6ast1an
is this based on florents code?
17:26
anuejn
ah nice
17:26
Bertl
nope, it's from scratch
17:26
se6ast1an
could florent help at this point in any way?
17:26
Bertl
having some trouble with my logic analyzer at the moment, but I'm confident I can sort this out
17:27
Bertl
se6ast1an: probably but till now his messages have been cryptic and not very useful
17:27
se6ast1an
well we could attempt a chat session if that would potentially help
17:28
se6ast1an
but lets discuss that afterwards
17:28
Bertl
maybe, I'm open to it but we should wait till we have some results
17:28
se6ast1an
right
17:28
Bertl
doesn't make much sense to discuss code which isn't finished yet and has not produced any data
17:29
_florent_
Bertl, se6ast1an: hi, yes sorry for not being very present/helpful, i was busy on others things...
17:29
Bertl
ah, nice to see you're around ... just saw the USB working on ECP5 and Xilinx
17:29
vup
Bertl: as far as i can tell, the ftdi library is also based on libusb, do you think there is a lot of performance to gain by writing a "better" libusb receiver?
17:30
Bertl
_florent_: care to elaborate what devices those are?
17:30
Bertl
vup: no idea, but I prefer to eliminate the FTDI driver to see where the real problems are
17:30
_florent_
Bertl: i'm trying to get USB3 working with just the transceivers, on Kintex7/Artix7 and ECP5
17:30
vup
Bertl: i see
17:31
Bertl
_florent_: tranceivers means MGTs, yes?
17:31
Bertl
so the ECP5 is one of the high end SERDES devices not just any old ECP5U or so
17:32
_florent_
Bertl: that's still very experimental, but while doing that, i probably found some reasons why LiteSATA code was not working correctly on Artix7, so want to do a test soon (so with your module)
17:33
_florent_
Bertl: yes, the high speed transceivers (GTX on Kintex7, GTP on Artix7, SERDES on ECP5)
17:34
_florent_
Bertl: i also ordered a CameraLink 4K and received it today :)
17:34
anuejn
_florent_: is there any chance to get USB 3.1 Gen 2 (10gbit/s) working with that?
17:34
Bertl
_florent_: okay, tx, because the ECP5 with serdes is not supported by the 'free' Lattice tools ...
17:35
Bertl
i.e. that is completely handled by the open source toolchain I presume?
17:35
_florent_
Bertl: i have Diamond installed, but i mostly no longer use it since the open-source toolchain is working fine
17:36
anuejn
bc. there is no silicon that implements fifo to usb3 at that speed i know of :(
17:36
_florent_
anuejn: i need to have a look at USB3.1, but at least USB3.0 is a first step and things should not be completely different
17:37
Bertl
well, USB 3.0 on an ECP5 plugin module would be quite nice, especially with isochronous transfers :)
17:38
vup
3.1 gen2 has a signaling rate of 10Gbit/s which is not doable with the ECP5 serdes afaik
17:38
_florent_
vup: yes, it will only work with high end FPGAs (Kintex7 for example)
17:39
vup
but there is 3.2 Gen1x2 , which would be basically two 3.0 links afaik
17:42
Bertl
okay, so there is a lot of potential interesting stuff ...
17:43
Bertl
continuing with my report (more on the USB/camlink later I guess)
17:43
Bertl
I also finished a prototype board for the TLK10232 chip
17:44
Bertl
(this was found as an interesting alternative option to conenct the Beta with a PC)
17:44
Bertl
again this is based on the TE714 module from Trenz (mainly to save cost and reuse)
17:45
Bertl
and it is done as PCIe x4 plugin card with a USB-C conenctor for data transfer between two boards
17:46
Bertl
I've connected all data lines on the low and high speed side
17:46
Bertl
so that's much more than we can actually use as an AXIOM Beta plugin but for testing that should be perfect
17:46
Bertl
the board also works stand alone without any PCIe again to simplify testing
17:47
Bertl
s/works/is designed to work/ :)
17:47
anuejn
Bertl: would it be possible to do real 10G ethernet with that chip?
17:47
Bertl
yes, why not
17:48
Bertl
finally on the Power Board side we figured that we want to make some minor changes for the ABCP
17:49
Bertl
we decided to get rid of the FTDI there which was intended for easy JTAG and I2C debugging, but nobody used it yet and it's a lot of board space with little gain (especially if not used)
17:49
Bertl
you can still connect the JTAG on the MicroZed directly and we will have some test points or connector for I2C
17:50
Bertl
the freed-up board space will probably be used for a switching pre-regulator which can handle typical battery voltages
17:51
Bertl
i.e. anything between 6V and 15V or so
17:51
Bertl
I guess that's it from my side for this week
17:52
se6ast1an
the swticher board will be separate at first though and the reason for it is enabling using 12V fans in the compact
17:52
se6ast1an
great thanks for the report
17:52
se6ast1an
anyone else with anything to report?
17:52
anuejn
Bertl: re 10G ethernet but not in a typical plugin module situation? bc the ic can to at max 1:4 serdes and that would require 2.5 gbit coming out of the zync?
17:53
Bertl
correct
17:53
Bertl
we are aiming at 4x 1.5Gbit two channels for the plugin
17:55
anuejn
ah ok i see
17:55
anuejn
thats a bit sad but maybe the only viable way
17:57
Bertl
10G ethernet might still be an option for a later time
17:57
Bertl
i.e. assuming we use a MGT capable 7 series or ECP5 we could also use the single version (or just one channel) at full speed
17:58
BAndiT1983
changed nick to: BAndiT1983|away
18:02
se6ast1an
ok anything else, or meeting concluded?
18:02
anuejn
ah nice
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BAndiT1983|away
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BAndiT1983
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se6ast1an
off to bed
21:25
se6ast1an
good night
21:26
apurvanandan[m]
good night :)
21:44
a13b
I'm watching the latest video. What's a "push button"?
21:44
Bertl
a 'button' you can 'push'
21:45
apurvanandan[m]
XD
21:45
Bertl
the 'slide button' OTOH is a little confusing, as it should be a 'slide switch'
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