#apertus IRC Channel Logs

Morning folks, how is it going?

good day

https://www.apertus.org/axiom-team-talk-15-2-gsoc-axiom-remote-article-december-2019

anuejn: please go ahead!

great, screenshot?

it now has a fancy landing page that shows a howto ssh connection and general explanation

(as se6ast1an suggested)

good point, generral introduction woul make sense I guess

it is called nctrl

it can be used with the beta and the micro and is configured via yml files

https://github.com/axiom-micro/webui

https://github.com/apertus-open-source-cinema/axiom-beta-firmware/pull/127

most excellent

i think thats it :)

note that lua scripting is being reworked at the moment, so the current api / look is not what it will be like after that

great

noted

you saw the TT15.2 release today already

we ordered an all new compact enclosure set of cnc milled parts

I will now with the cnc parts done for now focus on the remote software again

need to understand where we are now got get started

thats it from me

well

and it looks like the device can be put into the default fx3 mode where firmware can be uploaded

still unlcear is whether the FPGA has encryption enabled and/or is locked down, so that's something to figure out

on the USB3 plugin side we now have a (hopefully working) test HDL code to emulate various write patterns and evaluate the throughput from the FPGA side

https://twitter.com/GregDavill/status/1202498159093485568

btw, some other people seem to be investigating the cam link 4k aswell, this thread has some nice images without the chips: https://twitter.com/GregDavill/status/1203998610775371776

any more cam link related infos/questions/etc?

so back to the USB3 plugin then :)

this is implemented as a jtag configurable unit where you can set all the test parameters and read out performance counters

the HDL code on the FPGA side

so it allows for modes where data is only transferred when the fifo is not full as well as generic write always (potentially with data loss) and does accounting based on the feedback from the FTDI

yes, obviously I am :)

is this based on florents code?

nope, it's from scratch

having some trouble with my logic analyzer at the moment, but I'm confident I can sort this out

well we could attempt a chat session if that would potentially help

maybe, I'm open to it but we should wait till we have some results

doesn't make much sense to discuss code which isn't finished yet and has not produced any data

ah, nice to see you're around ... just saw the USB working on ECP5 and Xilinx

_florent_: care to elaborate what devices those are?

Bertl: i'm trying to get USB3 working with just the transceivers, on Kintex7/Artix7 and ECP5

_florent_: tranceivers means MGTs, yes?

Bertl: that's still very experimental, but while doing that, i probably found some reasons why LiteSATA code was not working correctly on Artix7, so want to do a test soon (so with your module)

Bertl: i also ordered a CameraLink 4K and received it today :)

_florent_: okay, tx, because the ECP5 with serdes is not supported by the 'free' Lattice tools ...

Bertl: i have Diamond installed, but i mostly no longer use it since the open-source toolchain is working fine

anuejn: i need to have a look at USB3.1, but at least USB3.0 is a first step and things should not be completely different

3.1 gen2 has a signaling rate of 10Gbit/s which is not doable with the ECP5 serdes afaik

but there is 3.2 Gen1x2 , which would be basically two 3.0 links afaik

continuing with my report (more on the USB/camlink later I guess)

(this was found as an interesting alternative option to conenct the Beta with a PC)

and it is done as PCIe x4 plugin card with a USB-C conenctor for data transfer between two boards

so that's much more than we can actually use as an AXIOM Beta plugin but for testing that should be perfect

s/works/is designed to work/ :)

yes, why not

we decided to get rid of the FTDI there which was intended for easy JTAG and I2C debugging, but nobody used it yet and it's a lot of board space with little gain (especially if not used)

the freed-up board space will probably be used for a switching pre-regulator which can handle typical battery voltages

I guess that's it from my side for this week

great thanks for the report

Bertl: re 10G ethernet but not in a typical plugin module situation? bc the ic can to at max 1:4 serdes and that would require 2.5 gbit coming out of the zync?

we are aiming at 4x 1.5Gbit two channels for the plugin

thats a bit sad but maybe the only viable way

i.e. assuming we use a MGT capable 7 series or ECP5 we could also use the single version (or just one channel) at full speed

ok anything else, or meeting concluded?

good night

I'm watching the latest video. What's a "push button"?

XD