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#apertus IRC Channel Logs

2018/05/09

Timezone: UTC


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ymc98
Bertl : Can we discuss the limiting parameters of the protocol?
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05:11
ymc98
Bertl : This is a link to a paper I found online for inter-fpga communication and error correction. I'd like to know if this is suitable for our purposes. https://drive.google.com/open?id=1-9r3mRJ8aLwDKwKp5StMqOcKi8VaH4DG
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se6astian|away
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08:06
Bertl_zZ
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08:06
Bertl
morning folks!
08:14
Bertl
ymc98: give me 10 minutes and I should be ready for a protocol discussion
08:16
Bertl
@paper: well, they use a 33+ signal bus, so that's not an option for us, besides that it seems to be designed as a multi drop system or so and we only have/want a master/slave connection
08:16
Bertl
nevertheless, the basic principles are all the same for FPGA to FPGA communication
08:53
Bertl
ymc98: you still around?
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10:19
Bertl
ymc98: see irc logs
10:58
ymc98
Bertl : I have seen the logs. I also would like to know the tool required. I am familiar Vivado. I don't know the design tools required for MachXO2.
11:00
ymc98
Also, I'd like to know how I can have hardware access to the boards.
11:02
Bertl
okay, so Vivado for Zynq and Diamond for the MachXO2
11:03
Bertl
we have a remote system available where you can test on (currently shared with other students)
11:03
ymc98
I would also like to know the data specifications that Zynq outputs
11:04
Bertl
what I need to get from you is an ssh key (for the access)
11:04
Bertl
yes, we should have a talk about the protocol and how to make it efficient
11:06
ymc98
I will provide that to you shortly. I will start implementing 8b10b code and the checksum for the incoming data.
11:07
Bertl
yes, 8/10 encoding is a good idea for the physical layer transport
11:07
Bertl
it might also be a good idea to think about 'idle' states
11:08
Bertl
i.e. what happens when nothing needs to be transported
11:12
ymc98
some handshaking can be implemented between Zynq and MachXO2.
11:12
ymc98
Is this a good way to take care of idle states?
11:13
Bertl
maybe, we'll see ... the main reason to consider idle states is to reduce power consumption
11:15
Bertl
we have a common clock between Zynq and MachXO2 so it shouldn't be a problem with synchronization when pausing the data flow
11:15
Bertl
but this is just some input to keep in mind
11:16
Bertl
IMHO first step is to get a reliable communication working
11:16
Bertl
then we can see how to use it efficiently
11:20
ymc98
Absolutely
11:22
ymc98
Should static timing analysis be performed?
11:22
ymc98
Before the first evaluation.
11:24
Bertl
I would say it is good practice not to run any designs which didn't pass timing checks
11:25
Bertl
both Vivado and Diamond do static timing analysis during implementation so that shouldn't be a problem
11:25
Bertl
the only thing you need to be careful about is 'describing' the timing constraints properly
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12:36
danieel
if you consider on/off for the channel, it might be easier to go with dedicated train/ready signals. But any wakeup will add some latency (in worst case of unexpected duration, like a pll startup)
12:36
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12:37
danieel
is there any need to go for async? a regular ddr sync lvds could do ~ 400mbit, and it would be clocked just from source (no fancy 8/10 high speed lvds)
12:38
danieel
anyway 8b10b for me seems unnecessary - there is no need to ac coupling, nor clock recovery
12:41
Bertl
8/10 encoding can also serve to increase the bandwidth
12:41
danieel
above the 1.25G for regular ioserdes/lvds?
12:41
Bertl
(by reducing the transitions and thus the noise)
12:41
danieel
that AC spec is not related to 8b10b..
12:42
Bertl
think TMDS
12:42
danieel
that is rather a solution for interference/coupling over long cables, there is no tmds for short/internal busses
12:43
Bertl
but yes, it is not sure that 8/10 encoding (or scrabling) is required or useful
12:43
Bertl
we'll see
12:43
danieel
what about sync clocking?
12:43
danieel
(sort of mipi way - sample on edges, with discontinuous clock)
12:44
danieel
for low power consideration
12:44
Bertl
we have a common clock but it is not sure how well the LVDS channels align to that
12:44
Bertl
needs to be tested as well
12:45
Bertl
but stopping the clock is not a good idea
12:45
Bertl
(in our case)
12:45
danieel
if the bitrate is low enough, it can be captured directly (we do on A7 up to 600mbit ~ 300mhz ddr)
12:45
danieel
why?
12:45
Bertl
because it is common for both MachXO2 s
12:46
danieel
the other one could clock in idle (byte sync) symbols :)
12:47
Bertl
yeah, having low transition idle symbols is definitely one option
12:48
danieel
how fast the XO2 can do sync receive/transmit (without PLL) ?
12:49
Bertl
probably up to 300MHz but I don't know (the datasheet should have some clues)
12:54
danieel
262 / 315 / 378 MHz by speed grade, with DDR4 input
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se6astian
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Bertl
off for now ... bbl
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Bertl
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BAndiT1983|away
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BAndiT1983
hi supragya, also long time no see
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18:04
supragya
BAndiT1983: hi :)
18:04
BAndiT1983
hi supragya
18:04
supragya
been caught up in a few things, nothing much, how's it going?
18:05
BAndiT1983
not much, some adjustements for OC, but now some work has to be done for daemon
18:05
BAndiT1983
*adjustments
18:06
supragya
hmm, just recieved the apertus newsletter (yesterday)... good to see it finally working
18:06
BAndiT1983
any new progress on raw container?
18:06
BAndiT1983
guys did it manually, switch from MJML to some templating system would be better, but currently gsoc has priority
18:06
supragya
I am currently looking at the two ways g3gg0 told me I could take
18:07
supragya
to change MLVFS or to change the bit encoding
18:07
BAndiT1983
which ways? could read the logs, but don't want to distract myself from daemon
18:07
BAndiT1983
ah, this stuff, don't know what's better
18:07
supragya
that's what I am auditing right now..
18:07
BAndiT1983
either way requires more computation on PC side
18:08
supragya
which is what we have
18:08
supragya
the issue is... which would be easier and would make more sense to do
18:08
supragya
to change MLVFS or to change the bit encoding to canon
18:08
BAndiT1983
we should use native bit order of zynq/ARM
18:09
supragya
hmm
18:09
supragya
is PLR used in video capture too?
18:09
supragya
HDR settings?
18:09
BAndiT1983
what do you mean?
18:11
supragya
remember the meeting?
18:11
supragya
g33g0 asked of some weird gamma curve...
18:11
supragya
AXIOM camera have...
18:12
supragya
It should be only the case when PLR is used (multiple exposure)
18:12
supragya
(maybe I could be wrong)...
18:13
supragya
that's for HDR (Bertl told me PLR was used in camera, not dual ISO)
18:13
supragya
so, is that mechanism for single frame shoot? or can be even used in videos... I am wondering
18:14
BAndiT1983
i suppose for videos, see newest hdr video development
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18:14
supragya
any links to refer BAndiT1983 ?
18:14
BAndiT1983
http://www.cmosis.com/news/press_releases/cmosis_shows_upgraded_cmv12000_offering_300_fps_at_full_resolution
18:16
supragya
will look into it... got to go sleep (12 here)
18:16
supragya
have a great night ahead, BAndiT1983 :)
18:16
BAndiT1983
good night
18:17
BAndiT1983
ah, TofuLynx is also here
18:17
TofuLynx
Hello :)
18:17
BAndiT1983
what's the latest news?
18:17
TofuLynx
nothing much, studied for university and did gym, now I am home
18:18
TofuLynx
I wanted to talk with you regarding that git practise with development branches and also regarding the task I finished
18:19
BAndiT1983
ok, go on
18:20
TofuLynx
basically, if I understood correctly, I will create a new branch for every feature I wish to implement, and then I delete the branch when the feature is implemented and fully functional and mergend onto master.
18:20
BAndiT1983
not master, but dev
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supragya
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18:21
BAndiT1983
usual practice is, that dev branch is used for development and stable commits pushed to master, whne features or fixes are ready
18:21
TofuLynx
yeah, but the link you gave goes more to the extreme
18:21
BAndiT1983
feature branch is another practice which allows to work in bigger teams without interferences between developers
18:21
BAndiT1983
i know, the link was an example
18:22
TofuLynx
What do you prefer?
18:22
TofuLynx
for our case the dev branch is more suited?
18:22
TofuLynx
as we are a small team
18:22
BAndiT1983
from my experience, yes
18:23
TofuLynx
Ok, we have to update the dev branch then :)
18:23
BAndiT1983
as in the future the master branch has to be stable, so we will focus on dev branch and feature branches
18:24
TofuLynx
yeah.
18:24
TofuLynx
Did you check the unit test?
18:26
BAndiT1983
travis ci has ;)
18:26
BAndiT1983
just looked through it quickly, as i was at work, when i saw your PR
18:26
BAndiT1983
looks good, but more thorough check will be done later, has to do some daemon re-work
18:27
TofuLynx
I have some questions regarding the catch
18:27
TofuLynx
how do you choose the test you wish to run?
18:31
BAndiT1983
it executes all the tests it finds
18:32
BAndiT1983
or one can also execute just groups, but haven't looked further yet, as we don't have many at the moment
18:33
TofuLynx
I had some problems with it, as I was getting segfault with pre processor
18:36
BAndiT1983
you can debug through it relatively comfortable, using qtcreator for it
18:37
BAndiT1983
also segfaults are a problem, because of some whacky implementations there
18:37
BAndiT1983
will restructure even more in the next time
18:37
BAndiT1983
have you tried to activate travis ci for your repo yet?
18:38
TofuLynx
it's activated, yes
18:39
BAndiT1983
alright, now you should try to activate it for dev branch, so we are on the same setup, more or less
18:40
BAndiT1983
you can just trigger a new build and select dev
18:40
TofuLynx
roger, should I update the dev branch?
18:41
BAndiT1983
which way?
18:42
TofuLynx
what do you mean by which way?
18:42
BAndiT1983
what do you mean by update? ;) just asked how you want to update it
18:43
TofuLynx
ah xD put it on par with master branch
18:44
BAndiT1983
can do it for main repo a bit later, but you can do it for your fork already
18:44
BAndiT1983
so, off for a bit to get some stuff
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BAndiT1983
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18:45
TofuLynx
ok :)
19:08
TofuLynx
I will be right back, going to dinner
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BAndiT1983|away
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TofuLynx
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20:29
TofuLynx
Hello
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illwieckz
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RexOrCine
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TofuLynx
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21:07
TofuLynx
BAndiT1983:
21:07
TofuLynx
So, what is my next task?
21:07
BAndiT1983
what would you prefer to do next?
21:08
BAndiT1983
btw. currently doing PR for dev sync, just waiting for travis
21:08
TofuLynx
I think finishing the debayer class
21:09
BAndiT1983
debayer is ok, but we should look further, as debayer will be a continuous story
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illwieckz
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21:12
BAndiT1983
hm, travis seems to be very busy at the moment, build does not start
21:13
TofuLynx
I meant the bilinear debayer
21:13
TofuLynx
So I can be behind schedule according to my proposal
21:20
se6astian
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21:23
BAndiT1983
general functionality should be done within timeline, if possible
21:23
TofuLynx
what is general functionality?
21:23
BAndiT1983
but bells and whistles, when some spare time is available
21:23
BAndiT1983
correct debayering
21:24
TofuLynx
ah okk
21:24
TofuLynx
Hmm, what do you suggest to do?
21:24
BAndiT1983
let me check the proposal
21:24
BAndiT1983
what about trello board?
21:24
TofuLynx
hmm
21:26
BAndiT1983
ok, i see base debayer class, not a bad idea, but needs some investigation
21:26
BAndiT1983
my idea was, to move conversion from 12 to 16bit to specific image loader classes
21:26
BAndiT1983
as they should take care of it, depending on the needs of the related format
21:27
BAndiT1983
our source would be a data array with image data and debayer classes would split it to RGB and fill in the buffers of OCImage
21:28
BAndiT1983
or to be precise, later they would request the buffer from static allocator and just assign the pointer to ocimage
21:29
BAndiT1983
TofuLynx, also the tests for bilinear debayer have to be implemented, e.g. with special or error cases
21:29
BAndiT1983
but this is also continuous process, tests will be added in the course of gsoc
21:30
TofuLynx
Yeah I agree with that
21:30
TofuLynx
I left some "blank days" for code improvement
21:31
TofuLynx
You basically want to convert 12 to 16 bits in the imageLoader class?
21:31
BAndiT1983
we still have some days left, before gsoc coding starts oficially, although google allows to start before it, so you can choose your task freely for that period
21:31
BAndiT1983
yes, so we have always the same base for debayer stuff, without jumping forth and back
21:32
BAndiT1983
what about 2 pools, one for final frames and one for raw data arrays?
21:33
TofuLynx
why do you need a pool for raw data arrays?
21:34
BAndiT1983
so the stuff can be processed in parallel
21:34
BAndiT1983
this would allow to load multiple files in parallel
21:37
TofuLynx
for what purposes?
21:43
BAndiT1983
faster video sequence loading?
21:43
BAndiT1983
while first array is processed, second one is loaded and can be processed, maybe also third one, depends on the system, then first one will be removed and replaced by 4th frame data and so on
21:48
TofuLynx
Interesting, I can see the advantages
21:48
TofuLynx
So, we have to implemente the pool allocator
21:49
BAndiT1983
yep, started to test the memory lib last week, but had to stop in favor of other stuff for gsoc and apertus
21:49
BAndiT1983
so, off for today, see you
21:49
BAndiT1983
changed nick to: BAndiT1983|away
21:53
TofuLynx
See you!
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TofuLynx
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23:27
Bertl_oO
off to bed now ... have a good one everyone!
23:27
Bertl_oO
changed nick to: Bertl_zZ