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#apertus IRC Channel Logs

2019/04/09

Timezone: UTC


00:01
Bertl
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/mfug_ddio.pdf
00:02
Ashu
Bertl, I have proposed for .dib file as container for visualisation pipeline.
00:02
Bertl
Ashu: okay?
00:03
Bertl
aSobhy: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/cyc/cyc_c51010.pdf
00:04
futarisIRCcloud
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00:04
Ashu
hoping to get draft review,
00:05
Bertl
what is a .dib file (besides a container) and how does it fit into the pipeline?
00:06
Ashu
A device-independent bitmap (DIB) is a format used to define device-independent bitmaps Using it store overlay before rendering
00:06
aSobhy
but the worst path has a slack of -0.197 !
00:07
aSobhy
ok I'll see those links
00:08
Bertl
those are just what I found on a quick google search
00:09
Bertl
note: we are not using any of the Intel (former Altera) FPGAs yet, so I have no detailed experience with them
00:09
Bertl
but the Cyclone IV handbook lists LVDS speeds of up to 640Mbps
00:10
Bertl
and in the higher speed classes up to 875Mbps
00:11
Bertl
so there are certainly ways to get that amount of data into and out of the chip
00:11
Bertl
Ashu: okay, but what do you mean with image pipeline?
00:14
Ashu
Image Acquisition Pipeline: which provides data in memory.
00:15
Bertl
somehow I'm lost ... where is your proposal so that I can read it and get a clue?
00:15
aSobhy
Okay I hope I could finished it soon
00:15
aSobhy
finish*
00:16
apurvanandan[m]
Whom? mine?
00:16
Ashu
PM you.
00:17
Bertl
apurvanandan[m]: when somebody writes without prefix: then it is usually an answer to the last person talking
00:17
Ashu
and I have also mailed to team mail and posted draft
00:20
Bertl
okay, now I have an idea what you are talking about
00:21
Bertl
well, the 'DIB' concept might be nice, but the ARM cores and the DDR memory is unlikely to be fast enough to get reasonable framerate this way
00:22
Bertl
i.e. when you want to do an overlay (like the histogram) then you definitely do not want to render it twice, i.e. once in a 'dib' container and then the 'dib' container to memory
00:22
Bertl
because the 'dib' container is also memory and thus has the same problems writing to the framebuffer has
00:24
Bertl
i.e. what you want to do is to have two (or several) renderers, e.g. one which generates the overlay direclty in the framebuffer memory and another one which generates SVG for the web client
00:24
Bertl
(SVG as instructions how to create the image not as bitmap) or even better to pass the histogram data to the web client and draw the entire image on the client side
00:27
Bertl
also note that the 'community bonding' phase is perfect to figure out stuff like existing tools (hist, snap, etc) if not done already earlier, so you do not need to reserve time after May 27th for that
00:33
Ashu
okay, will change visualisation section and yes,I have already figured how sensor tools are working, I was bit confused about implementing visualisation.
00:34
Bertl
currently the frame data is intermixed with the overlay
00:34
Bertl
i.e. you have 64bit words consisting of RG/GB data (12bit each) and overlay (16bit)
00:35
Bertl
this is likely to change in the future were we will split up frame data and overlay
00:35
Bertl
in any case, the overlay is located in memory at 'specific' addresses and similar to a file mapping this memory can be accessed from userspace
00:36
Bertl
so this is where you need to put any visualization which is supposed to appear on the preview monitor
00:37
Bertl
on the web side anything which doesn't consume too much resources (memory and CPU) is fair game
00:37
Bertl
(i.e. you want to push as much as possible to the client side)
00:42
Ashu
okay, these things makes sense and giving me direction, have to make lots of changes in a very short time .
00:44
Ashu
will do changes and submit it by today itself. Thanku
00:49
apurvanandan[m]
Bertl: If his proposal is viewed, please see my also :)
00:59
Ashu
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01:00
Bertl
no worries, I'm on it :)
01:02
Bertl
btw, you can also check each other's proposals and challenge tasks
01:02
apurvanandan[m]
I want to check, but how do I get access
01:03
Bertl
just ask and if they are interested, they will certainly share it with you
01:04
apurvanandan[m]
Ok I will ask with a few!
01:31
Bertl
okay, I'm through and will be off to bed shortly ... let me know if something is unclear
01:38
apurvanandan[m]
I have asked my questions in pm
01:41
aSobhy
Bertl, I wrote a dummy file with a single ddr register the result is the same as the FMAX is 780 MHz and also their is a restricted FMAX 250 with the same reason "limit due to minimum period restriction (max I/O toggle rate)"
01:42
aSobhy
in the FAQ of Intel fpga https://forums.intel.com/s/question/0D50P00003yyPPySAM/fmax-and-restricted-max
01:43
aSobhy
they are saying "There are different speed grades of chip, Like C1,2,3,4 etc. These will have restricted FMax because they are not as strict on testing the dies as the number increases. So C1 will have a higher restricted FMax than a C5"
01:43
aSobhy
but I can't find where those C1..5 can be selected !
01:44
Bertl
that's what I meant with different speed grades
01:44
Bertl
no idea how to select that on quartus, but should be easy to figure out with google's help :)
01:46
aSobhy
I am searching now but I want to tell you what I get as you said you are off to bed soon
01:46
aSobhy
so most probably it is a problem with the part not in my code ?
01:49
Bertl
both is possible
01:56
aSobhy
which tool you will run that design in order to check the max speed ? (marking the task)
01:57
Bertl
the one you specify in the make file
01:58
aSobhy
ok
01:58
Bertl
but do not worry too much about the limited fmax
01:58
Bertl
as long as the VHDL is fine you should be as well :)
02:02
Bertl
aSobhy: when you specify a device part, you usually include the speed grade, e.g.
02:03
Bertl
EP2C20F484C7 means package F484 and speed grade C7
02:04
aSobhy
okay
02:04
Bertl
(where C likely stands for commercial)
02:05
aSobhy
I haven't notice that :)
02:05
Bertl
live and learn! :)
02:05
Bertl
off to bed now ... have a good one everyone!
02:05
Bertl
changed nick to: Bertl_zZ
02:06
aSobhy
thaks Bertl, you relived me a bit :)
04:37
BAndiT1983|away
changed nick to: BAndiT1983
04:45
Dev_
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04:48
Dev_
Thank BAndiT1983 to your review prop, i will change the proposal those inconsistencies and submit it after college
04:48
BAndiT1983
no problem
04:48
Dev_
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05:00
mrohit[m]
hi BAndiT1983 , as discussed yesterday, the problem with sending data to daemon was how to send large number of parameters for each image sensor parameter such as the HDR mode etc....correct?
05:07
BAndiT1983
i still don't get the point out of technical view
05:08
BAndiT1983
which i've already described in the email, you descriptions are relatively vague and lack more precise descriptions
05:17
mrohit[m]
for eg. if we want to set HDR interleaved mode...we need 3 parameters:
05:17
mrohit[m]
time1 (defines exposure time for even columns), time2 (defines exposure time for odd columns), color (to choose between color and monochrome sensor)
05:17
mrohit[m]
the number of parameters can vary for all other settings (like exposure, subsampling etc.)
05:17
BAndiT1983
and?
05:17
BAndiT1983
why is it called time1 and time2? who teached you to call variables like that?
05:19
mrohit[m]
but daemon can accept a fixed number of values as currently value1 and value2 are received through flatbuffers
05:20
mrohit[m]
time1 and time2 are just for reference here, just for explaining, evenTime, oddTime will be better
05:20
BAndiT1983
and?
05:20
BAndiT1983
what has it to do with fixed number of values?
05:21
BAndiT1983
evenColumnTime would even be better and more readable
05:22
mrohit[m]
as we request to SetHDRInterleaved, we will need to provide 3 values, but flatbuffers can send only 2 at a time, as mentioned in the schema
05:22
BAndiT1983
seems like you miss the point there, we want to send single parameters to adjust the camera in real-time
05:25
mrohit[m]
you mean we don't need to set a setting such as HDR, rather we need to set individually the evenColumnTime, the oddColumnTime and color setting and enable the register for HDR?
05:25
BAndiT1983
for example
05:29
mrohit[m]
okay...seems like I was thinking in a wrong direction. So we just need to set those individual parameters...right?
05:29
mrohit[m]
But if a user just needs to set something at once, such as just selecting the HDR mode then isn't the daemon expected to figure out which registers to set for the correponding mode and set all of them?
05:30
BAndiT1983
this is where presets kick in
05:34
mrohit[m]
so for presets, do we use default parameter values, like fixed value for evenColumnTime, oddColumnTime? because flatbuffers cannot handle these many number of values, so we can't let user control these parameters while using presets..right?
05:35
mrohit[m]
for setting these individual parameters, we can have individual methods
05:35
mrohit[m]
And for a preset method, we can call those individual methods..I guess
05:35
BAndiT1983
what has it to do with flatbuffers?
05:36
BAndiT1983
sorry, but gsoc is about research and development, but not about me providing you with solutions for problems
05:38
mrohit[m]
okay, sorry for that, but I just want to know whether am I addressing the right problem
05:39
BAndiT1983
it's up to you to think about smart solution, but you are trying too hard and focus too much on flatbuffers, which is only there to send or retrieve settings
05:40
BAndiT1983
off to work
05:40
BAndiT1983
changed nick to: BAndiT1983|away
05:45
mrohit[m]
okay...thanks
05:45
mrohit[m]
I will work on the solution
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06:19
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07:15
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07:17
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07:44
se6astian|away
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08:07
nira
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08:14
nira
hi, I'm uploading my proposal and I have one more doubt. How do you want the challenge to be sent? Maybe a link to a GitHub repo, a Google Drive link, or something else?
08:18
parimal
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08:18
parimal
nira, a link to github repo would be the best
08:19
parimal
that's how everyone did it, also include the link of your repo in the proposal
08:21
parimal
BAndiT1983|away please do review my proposal today before the deadline :P
08:22
nira
ok, thank you!
08:23
parimal
no problem
08:24
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08:28
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08:37
apurvanandan[m]
Hi se6astian I had my proposal reviewed by Bertl twice and corrected it. I would be happy if you could also have a look at my proposal :)
08:47
se6astian
will do
09:01
se6astian
looks good, no further suggestions from my side
09:01
se6astian
but I don't know much about fpgas :)
09:25
nira
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09:34
apurvanandan[m]
Thanks :)
09:37
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11:06
Bertl_zZ
changed nick to: Bertl
11:06
Bertl
morning folks!
11:17
apurvanandan[m]
Good morning Bertl, I have corrected my proposal. If you have time ,please have one last review (if required) so that I can submit final PDF to GSoC.
11:19
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11:20
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11:49
Bertl
sure
11:51
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12:41
Bertl
apurvanandan[m]: Fares: aSobhy: what FPGA hardware do you have available right now and for the duration of GSoC 2019?
12:53
aSobhy
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12:57
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13:12
shivamgoyal
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13:34
aSobhy
thanks Bertl, I'll give you a message when i finished editing it :)
13:35
aSobhy
and can I have a look on the proposal that <se6astian> had mentioned it
13:36
aSobhy
to get more information i won't copy it :)
13:37
aSobhy
of course if the student is not in my year of participating :)
13:38
Fares
I have Z-turn lite board which has 7Z010 zynq.
13:38
Fares
thank you for the comments and the modifications Bertl
13:41
se6astian
aSobhy: you mean the one I mentioned yesterday? thats a current one I reviewed
13:42
aSobhy
ah okay, I have misunderstand
13:42
aSobhy
I think it's the project as mine but a previous year :)
13:52
Bertl
apurvanandan[m]: aSobhy: what FPGA hardware do you have available right now and for the duration of GSoC 2019?
13:53
Bertl
Fares: you're welcome! thanks for the hw info!
13:56
apurvanandan[m]
I have Virtex-5 XUPV5-LX110T board with XC5VLX110T-FF1136-3
13:58
Bertl
that is a nice piece of hardware :)
13:59
apurvanandan[m]
I know, I am proud of it. Our alumni donated us that.
14:02
Bertl
so what I think we can do to get you started is to send you two of the USB plugins together with a dual plugin breakout board (bunch of 2.54mm headers on that one) which you can easily connect to your FPGA board for testing
14:04
Bertl
this should allow for programming and testing the plugin modules on your hardware as well as preliminary testing of the FPGA-FPGA interface
14:07
apurvanandan[m]
Yes, this seems good place to start at :D
14:07
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14:08
saurabh_raj
Hi how is the qualification task code to be shared? Should I include a link to it in my proposal?
14:09
Bertl
yes, that would be the preferred way
14:09
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14:11
shivamgoyal
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14:12
Bertl
apurvanandan[m]: http://vserver.13thfloor.at/Stuff/AXIOM/BETA/PCIE_dual_breakout_2L_v0.2.{sch,brd}
14:12
Bertl
I take it you already found the USB 3.0 plugin board and schematic files
14:13
apurvanandan[m]
Yes , I have gone through them
14:14
shivamgoyal
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14:17
aSobhy
I don't have FPGA's :(
14:17
Bertl
no problem, just trying to figure out what is available where
14:18
Bertl
Fares: do you also have the IO Cape for the Z-turn lite?
14:18
aSobhy
ah okay :)
14:20
Bertl
aSobhy: do you have a benchtop power supply available (or can you borrow one for the duration of GSoC)?
14:21
shivamgoyal
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14:22
apurvanandan[m]
+
14:25
Fares
No I don't have the IO Cape but I can buy it if it is needed for the project.
14:25
Bertl
probably not required, again, just asking
14:26
aSobhy
also no but I will search for one and inform you if found ASAP :)
14:27
Bertl
thanks!
14:29
apurvanandan[m]
Bertl, by making bidirectional usb 3.0 probably we won't be sending video data to camera. We would be using it for controlling the video output, like brightness , contrast,etc.
14:29
apurvanandan[m]
Am I right?
14:29
Bertl
there are a number of optional use cases
14:30
Bertl
first there could be control signals (like in the UVC case)
14:30
Bertl
but we could also send image or overlay data at high speed to the camera
14:32
Bertl
this could even be useful in a bidirectional setup where the camera sends (reduced) image data to the PC which does some image processing/recognition/etc and sends back a an overlay to the camera which combines it with the high resolution live view
14:32
BAndiT1983|away
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14:41
Fares
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14:46
BAndiT1983
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14:49
aSobhy
Bertl, why their is encoding in the optimization while all FPGAs sharing the same CLK
14:49
aSobhy
?
14:51
Bertl
there are several ways to transfer data between ICs
14:52
Bertl
for low to medium speeds you can get away with source synchronous data which is simply clocked out on one IC and clocked in on the other
14:53
Bertl
with increasing data rates you need to have some way to synchronize the data with a clock (even if it is shared between both ends)
14:53
Bertl
there is also the problem that increased data rates result in a lot of noise and various problems for some data
14:54
Bertl
for example sending many '0' or '1' in a row causes the DC offset to get out of balance
14:54
Bertl
or sensing a constant sequence of '010101...' will produce a rather high frequency switching and thus a lot of noise and potential interference
14:55
Bertl
for all those reasons you usually encode the data in some way which mitigates the problems (8b/10b or TMDS or similar)
14:56
aSobhy
OK got it :)
14:56
Bertl
you also need to do link training as the actual 'delay' on the data lines starts to escape the tolerances of static analysis
14:56
Bertl
(the variation on the delay)
14:57
aSobhy
link train at every setup? am I right !
14:57
aSobhy
training*
14:57
Bertl
for the RF (Routing Fabric) communication there are some additional subtle requirements which need to be investigated and addressed
14:58
Bertl
for example: how to handle phases where there is no communication at all
15:01
aSobhy
mmm okay
15:02
aSobhy
adding it to my note
15:02
Bertl
i.e. something like 'moderate power saving' or 'reducing noise' et
15:02
Bertl
*etc
15:04
Bertl
link training (this might also interest apurvanandan[m]) needs to be done at the beginning but is best handled/repeated during idle periods
15:05
Bertl
or if possible, link delay adjustments can be done during normal operation
15:06
Bertl
(the reason why this is useful is because timing is also affected by the environment, like temperature, noise, power, etc)
15:10
aSobhy
Sounds good I'm really excited
15:13
se6astian
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15:21
apurvanandan[m]
I added the third stretch goal as well ( not went into details). You can have a look if you want.
15:22
Bertl
will do shortly
15:28
aSobhy
Is it a task to do a power consumption test of the modules I'll make ?
15:29
Bertl
we will have to test a bunch of things including power consumption and try to optimize the solution (or make it generic enough to be suitable for different cases)
15:30
Bertl
power consumption is rather simple to measure on the AXIOM Beta (we have a lot of instrumentation in this regard) but of course preliminary power budget calculations (as done by many tools) helps too
15:31
aSobhy
Ok that's would be in the optimization task of every module i'll add it
15:31
Bertl
we also need to investigate the effect on other parts of the camera and limit noise
15:33
aSobhy
and also that point
15:44
apurvanandan[m]
Bertl, In proposal details on GSoC page do we need to write 1200 characters?
15:45
apurvanandan[m]
I just have written 200 characters
15:45
apurvanandan[m]
Please take a look their also
15:45
Bertl
we (apertus) do not care much about that, a short version is perfectly fine, no idea what google expects though
15:46
apurvanandan[m]
OK, thank you. I am going to upload the final PDF now :)
15:48
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15:55
Bertl
btw, I almost forgot to mention (this year):
15:56
Bertl
please add a proper copyright and license (open source compatible) information to your challenge code
15:58
apurvanandan[m]
Ok adding it now.
16:01
aSobhy
Bertl, Can you have a look I have done changes :)
16:02
BAndiT1983|away
changed nick to: BAndiT1983
16:06
aSobhy
Ok I'll add them
16:11
apurvanandan[m]
Going offline now , haven't slept for two nights. ^^'
16:11
apurvanandan[m]
I have submitted the proposal. Also added the GNU LICENSE file.
16:15
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16:15
parimal
BAndiT1983, is that you as redfalcon?
16:16
RexOrCine|away
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16:17
BAndiT1983
parimal, yes
16:18
BAndiT1983
i miss some more on technical info how you would solve the task, as your proposal only describes things we've discussed in the chat
16:19
BAndiT1983
a proposal, at least in my opinion, should provide a little bit more in-depth info on how the task will be approached, which obstacles could occur and how it would be prevented
16:20
BAndiT1983
you write a lot about discussing, but GSoC is about research and development, where the students should be able to wrk on their own and mentor guiding
16:20
BAndiT1983
*work
16:20
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16:20
BAndiT1983
it's not about me explaining to you how to solve the task, in this case i can also sit down by myself and implement modules
16:22
parimal
yes I agree, obviously it will be me doing the research
16:24
parimal
I understand what needs to be done but I thought the in depth "how" part I can do later as I study it more
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16:28
parimal
thanks for the review, I will see what I can update in the remaining time :)
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se6astian|away
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17:04
aSobhy
Bertl, l have submitted the final proposal their still an hour so if their is any issue with the newly added tasks to the timeline please tell me :)
17:05
Bertl
did you submit it only as final or is it the same as the latest draft?
17:05
Bertl
(because we cannot see the final proposals yet)
17:06
BAndiT1983
changed nick to: BAndiT1983|away
17:07
Bertl
btw, you want to put a copyright notice together with some license information in each of your files
17:08
Bertl
check the existing project files (apertus) for examples
17:11
aSobhy
It is the same link of the draft that i sent you earlier
17:17
nira
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17:18
Bertl
yeah, well, a lot of copy and paste (with a lot of copy and paste errors :)
17:20
Bertl
but it looks reasonably good to me .. if you really want to add something then make an example section where you propose a design or discuss the pros and cons of this or that protocoll
17:21
aSobhy
you caught me :)
17:23
aSobhy
I wish I could do that but I haven't finished the do file yet
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17:38
RexOrCine
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17:54
Dev_
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nira
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17:55
Bertl
wb nira! you might consider getting a proper IRC client instead of using the web client (which has a number of issues)
17:56
Bertl
(there are a bunch of good clients out there like Pidgin, irssi, HexChat, Koversation, etc)
17:56
Dev_
I have also submitted the final proposal !
17:57
Bertl
just in time :)
17:57
Dev_
How many proposal org received this year , just curious ??
17:58
Dev_
Yes Bertl :)
17:58
Bertl
22 so far
17:59
Dev_
Is it more than last years , i guess .
17:59
nira
yes, just today I was looking to do it, thank you!
17:59
Bertl
Dev_: I do not remember the numbers from last year but it was about the same
18:00
RexOrCine|away
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18:00
RexOrCine
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18:00
Dev_
Okay :) , thank you
18:00
Dev_
Bertl
18:01
Dev_
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18:01
Bertl
also a word of advice: the next period is a good chance to convince the mentors that you are the best choice for the task you proposed :)
18:02
Bertl
this is usually achieved by working with the community, collecting information, asking smart and on-topic questions and making suggestions or other contributions
18:11
Ashu
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