#apertus IRC Channel Logs

Bertl, I have proposed for .dib file as container for visualisation pipeline.

aSobhy: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/cyc/cyc_c51010.pdf

hoping to get draft review,

A device-independent bitmap (DIB) is a format used to define device-independent bitmaps Using it store overlay before rendering

ok I'll see those links

note: we are not using any of the Intel (former Altera) FPGAs yet, so I have no detailed experience with them

and in the higher speed classes up to 875Mbps

Ashu: okay, but what do you mean with image pipeline?

somehow I'm lost ... where is your proposal so that I can read it and get a clue?

finish*

PM you.

and I have also mailed to team mail and posted draft

well, the 'DIB' concept might be nice, but the ARM cores and the DDR memory is unlikely to be fast enough to get reasonable framerate this way

because the 'dib' container is also memory and thus has the same problems writing to the framebuffer has

(SVG as instructions how to create the image not as bitmap) or even better to pass the histogram data to the web client and draw the entire image on the client side

okay, will change visualisation section and yes,I have already figured how sensor tools are working, I was bit confused about implementing visualisation.

i.e. you have 64bit words consisting of RG/GB data (12bit each) and overlay (16bit)

in any case, the overlay is located in memory at 'specific' addresses and similar to a file mapping this memory can be accessed from userspace

on the web side anything which doesn't consume too much resources (memory and CPU) is fair game

okay, these things makes sense and giving me direction, have to make lots of changes in a very short time .

Bertl: If his proposal is viewed, please see my also :)

no worries, I'm on it :)

I want to check, but how do I get access

Ok I will ask with a few!

I have asked my questions in pm

in the FAQ of Intel fpga https://forums.intel.com/s/question/0D50P00003yyPPySAM/fmax-and-restricted-max

but I can't find where those C1..5 can be selected !

no idea how to select that on quartus, but should be easy to figure out with google's help :)

so most probably it is a problem with the part not in my code ?

which tool you will run that design in order to check the max speed ? (marking the task)

ok

as long as the VHDL is fine you should be as well :)

EP2C20F484C7 means package F484 and speed grade C7

(where C likely stands for commercial)

live and learn! :)

Thank BAndiT1983 to your review prop, i will change the proposal those inconsistencies and submit it after college

i still don't get the point out of technical view

for eg. if we want to set HDR interleaved mode...we need 3 parameters:

the number of parameters can vary for all other settings (like exposure, subsampling etc.)

why is it called time1 and time2? who teached you to call variables like that?

time1 and time2 are just for reference here, just for explaining, evenTime, oddTime will be better

what has it to do with fixed number of values?

as we request to SetHDRInterleaved, we will need to provide 3 values, but flatbuffers can send only 2 at a time, as mentioned in the schema

you mean we don't need to set a setting such as HDR, rather we need to set individually the evenColumnTime, the oddColumnTime and color setting and enable the register for HDR?

okay...seems like I was thinking in a wrong direction. So we just need to set those individual parameters...right?

this is where presets kick in

for setting these individual parameters, we can have individual methods

what has it to do with flatbuffers?

okay, sorry for that, but I just want to know whether am I addressing the right problem

off to work

okay...thanks

hi, I'm uploading my proposal and I have one more doubt. How do you want the challenge to be sent? Maybe a link to a GitHub repo, a Google Drive link, or something else?

nira, a link to github repo would be the best

BAndiT1983|away please do review my proposal today before the deadline :P

no problem

will do

but I don't know much about fpgas :)

Thanks :)

morning folks!

sure

apurvanandan[m]: Fares: aSobhy: what FPGA hardware do you have available right now and for the duration of GSoC 2019?

thanks Bertl, I'll give you a message when i finished editing it :)

to get more information i won't copy it :)

I have Z-turn lite board which has 7Z010 zynq.

aSobhy: you mean the one I mentioned yesterday? thats a current one I reviewed

I think it's the project as mine but a previous year :)

Fares: you're welcome! thanks for the hw info!

that is a nice piece of hardware :)

so what I think we can do to get you started is to send you two of the USB plugins together with a dual plugin breakout board (bunch of 2.54mm headers on that one) which you can easily connect to your FPGA board for testing

Yes, this seems good place to start at :D

Hi how is the qualification task code to be shared? Should I include a link to it in my proposal?

apurvanandan[m]: http://vserver.13thfloor.at/Stuff/AXIOM/BETA/PCIE_dual_breakout_2L_v0.2.{sch,brd}

Yes , I have gone through them

I don't have FPGA's :(

Fares: do you also have the IO Cape for the Z-turn lite?

aSobhy: do you have a benchtop power supply available (or can you borrow one for the duration of GSoC)?

+

probably not required, again, just asking

thanks!

Am I right?

first there could be control signals (like in the UVC case)

this could even be useful in a bidirectional setup where the camera sends (reduced) image data to the PC which does some image processing/recognition/etc and sends back a an overlay to the camera which combines it with the high resolution live view

Bertl, why their is encoding in the optimization while all FPGAs sharing the same CLK

there are several ways to transfer data between ICs

with increasing data rates you need to have some way to synchronize the data with a clock (even if it is shared between both ends)

for example sending many '0' or '1' in a row causes the DC offset to get out of balance

for all those reasons you usually encode the data in some way which mitigates the problems (8b/10b or TMDS or similar)

you also need to do link training as the actual 'delay' on the data lines starts to escape the tolerances of static analysis

link train at every setup? am I right !

for the RF (Routing Fabric) communication there are some additional subtle requirements which need to be investigated and addressed

mmm okay

i.e. something like 'moderate power saving' or 'reducing noise' et

link training (this might also interest apurvanandan[m]) needs to be done at the beginning but is best handled/repeated during idle periods

(the reason why this is useful is because timing is also affected by the environment, like temperature, noise, power, etc)

will do shortly

we will have to test a bunch of things including power consumption and try to optimize the solution (or make it generic enough to be suitable for different cases)

Ok that's would be in the optimization task of every module i'll add it

and also that point

I just have written 200 characters

we (apertus) do not care much about that, a short version is perfectly fine, no idea what google expects though

please add a proper copyright and license (open source compatible) information to your challenge code

Bertl, Can you have a look I have done changes :)

Ok I'll add them

I have submitted the proposal. Also added the GNU LICENSE file.

BAndiT1983, is that you as redfalcon?

parimal, yes

a proposal, at least in my opinion, should provide a little bit more in-depth info on how the task will be approached, which obstacles could occur and how it would be prevented

*work

it's not about me explaining to you how to solve the task, in this case i can also sit down by myself and implement modules

I understand what needs to be done but I thought the in depth "how" part I can do later as I study it more

Bertl, l have submitted the final proposal their still an hour so if their is any issue with the newly added tasks to the timeline please tell me :)

(because we cannot see the final proposals yet)

btw, you want to put a copyright notice together with some license information in each of your files

It is the same link of the draft that i sent you earlier

yeah, well, a lot of copy and paste (with a lot of copy and paste errors :)

you caught me :)

wb nira! you might consider getting a proper IRC client instead of using the web client (which has a number of issues)

I have also submitted the final proposal !

How many proposal org received this year , just curious ??

22 so far

yes, just today I was looking to do it, thank you!

Okay :) , thank you

this is usually achieved by working with the community, collecting information, asking smart and on-topic questions and making suggestions or other contributions