Current Server Time: 09:50 (Central Europe)

#apertus IRC Channel Logs

2019/10/08

Timezone: UTC


01:10
BAndiT1983|away
changed nick to: BAndiT1983
03:26
BAndiT1983
changed nick to: BAndiT1983|away
05:24
Bertl_zZ
changed nick to: Bertl
05:24
Bertl
morning folks!
05:24
apurvanandan[m]
Good morning
09:12
LordVan
joined the channel
11:37
Bertl
off for now ... bbl
11:37
Bertl
changed nick to: Bertl_oO
11:41
LordVan
left the channel
13:29
jhlink_
Morning~
13:46
danieel
left the channel
14:38
BAndiT1983|away
changed nick to: BAndiT1983
14:48
Spirit532
left the channel
14:48
Spirit532
joined the channel
15:10
danieel
joined the channel
17:18
BAndiT1983
changed nick to: BAndiT1983|away
18:51
namibj
jhlink_: afaik most of the fpga should be quite suitable for simulation/emulation. It might be quite slow, depending on what it ends up doing, but some of that should be fixable by running automated logic simplification over it to fuse purely-internal pipeline stages of at least a certain size of "functional block" into an abstraction that executes it in a single pipeline stage, and then just delays
18:51
namibj
output for as long as needed to match the original. This should then be more amenable for simulatiing/emulating on a "normal" CPU, because that logic's behaviour is quite far abstracted from the RTL implementation. I think this is called retiming, but I have no idea how easy it'd be to automate... Might want to consider if you don't want to wait for or buy the physical FPGA devboard.
23:47
RexOrCine|away
changed nick to: RexOrCine