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| 05:24 | Bertl | morning folks!
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| 05:24 | apurvanandan[m] | Good morning
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| 11:37 | Bertl | off for now ... bbl
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| 13:29 | jhlink_ | Morning~
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| 18:51 | namibj | jhlink_: afaik most of the fpga should be quite suitable for simulation/emulation. It might be quite slow, depending on what it ends up doing, but some of that should be fixable by running automated logic simplification over it to fuse purely-internal pipeline stages of at least a certain size of "functional block" into an abstraction that executes it in a single pipeline stage, and then just delays
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| 18:51 | namibj | output for as long as needed to match the original. This should then be more amenable for simulatiing/emulating on a "normal" CPU, because that logic's behaviour is quite far abstracted from the RTL implementation. I think this is called retiming, but I have no idea how easy it'd be to automate... Might want to consider if you don't want to wait for or buy the physical FPGA devboard.
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| 23:47 | RexOrCine|away | changed nick to: RexOrCine
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