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#apertus IRC Channel Logs

2019/10/08

Timezone: UTC


02:10
BAndiT1983|away
changed nick to: BAndiT1983
04:26
BAndiT1983
changed nick to: BAndiT1983|away
06:24
Bertl_zZ
changed nick to: Bertl
06:24
Bertl
morning folks!
06:24
apurvanandan[m]
Good morning
10:12
LordVan
joined the channel
12:37
Bertl
off for now ... bbl
12:37
Bertl
changed nick to: Bertl_oO
12:41
LordVan
left the channel
14:29
jhlink_
Morning~
14:46
danieel
left the channel
15:38
BAndiT1983|away
changed nick to: BAndiT1983
15:48
Spirit532
left the channel
15:48
Spirit532
joined the channel
16:10
danieel
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18:18
BAndiT1983
changed nick to: BAndiT1983|away
19:51
namibj
jhlink_: afaik most of the fpga should be quite suitable for simulation/emulation. It might be quite slow, depending on what it ends up doing, but some of that should be fixable by running automated logic simplification over it to fuse purely-internal pipeline stages of at least a certain size of "functional block" into an abstraction that executes it in a single pipeline stage, and then just delays
19:51
namibj
output for as long as needed to match the original. This should then be more amenable for simulatiing/emulating on a "normal" CPU, because that logic's behaviour is quite far abstracted from the RTL implementation. I think this is called retiming, but I have no idea how easy it'd be to automate... Might want to consider if you don't want to wait for or buy the physical FPGA devboard.
00:47
RexOrCine|away
changed nick to: RexOrCine