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#apertus IRC Channel Logs

2019/09/08

Timezone: UTC


06:31
se6ast1an
good day
06:57
BAndiT1983|away
changed nick to: BAndiT1983
06:59
Bertl_oO
off to bed now ... have a good one everyone!
06:59
Bertl_oO
changed nick to: Bertl_zZ
08:14
BAndiT1983
changed nick to: BAndiT1983|away
08:14
BAndiT1983|away
changed nick to: BAndiT1983
09:59
BAndiT1983
changed nick to: BAndiT1983|away
14:41
Bertl_zZ
changed nick to: Bertl
14:41
Bertl
morning folks!
14:41
apurvanandan[m]
Good morning
14:43
Bertl
hey apurvanandan[m]! how's going?
14:43
Bertl
+it
14:44
apurvanandan[m]
It is going well, how about you?
14:45
Bertl
it's fine too, tx!
14:46
apurvanandan[m]
I wanted to ask about the plan of action for removing the bug of data packets getting missed by the D3XX
14:46
apurvanandan[m]
How do you recommend to get to the root of problem
14:48
Bertl
well, the first step is to check with florent (or investigate his code) to see if that works better
14:50
apurvanandan[m]
Okay, those are in python
14:51
apurvanandan[m]
Also should we introduce some kind of feedback from MachXO2 to Zynq for pausing the data when fifo is full?
14:52
Bertl
that to some extend is an option, but requires enough total bandwidth
14:52
Bertl
i.e. we still need to keep the overall frame bandwidth
14:54
apurvanandan[m]
That means we will switch to control codes at same bandwidth and at MachXO2 we will ingnore those control codes
14:55
Bertl
hmm?
14:56
apurvanandan[m]
Like when the MachXO2 sends feedback that fifo is full, the Zynq will send some control code( which is not data) and at the MachXO2 we will know that data is paused.
14:57
Bertl
probably something like that
14:57
Bertl
the main problem will be to get a channel from the MachXO2 to the Zynq without compromising bandwidth
14:58
apurvanandan[m]
We can use the GPIOs?
14:58
Bertl
which are connected to the RF :)
14:59
apurvanandan[m]
:/
14:59
apurvanandan[m]
yes
15:00
Bertl
but yes, it is an option
15:00
apurvanandan[m]
Anyways, I firstly want to know the exact cause of the problem
15:00
Bertl
that said, it would be nice to get a reasonably reliable connection working without that
15:01
apurvanandan[m]
Which is still unclear till now
15:01
Bertl
yep, agreed
15:05
apurvanandan[m]
@florent were you able to do data transfer from the FT601 chip to the PC with the internal FIFOs in the MachXO2 overflowing?
15:06
apurvanandan[m]
_florent_
15:06
apurvanandan[m]
without*
17:11
BAndiT1983|away
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17:25
BAndiT1983
changed nick to: BAndiT1983|away
18:47
_florent_
Hi apurvanandan[m], i haven't tested the code on MachXO2, but the backpressure was handled yes (FIFOs could be full and propagate backpressure to FTDI or FPGA)
20:32
se6ast1an
off to bed
20:32
se6ast1an
good night
20:48
danieel
left the channel
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danieel
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21:11
danieel
left the channel
21:15
danieel
joined the channel
21:33
BAndiT1983|away
changed nick to: BAndiT1983
21:36
BAndiT1983
changed nick to: BAndiT1983|away