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| 04:48 | Bertl | off to bed now ... have a good one everyone!
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| 04:48 | apurvanandan[m] | Good night :)
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| 09:28 | namibj | I'm sorry I didn't yet write the email as I was told.
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| 14:00 | Bertl | morning folks!
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| 14:06 | se6ast1an | good day
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| 14:07 | se6ast1an | once you got your morning coffee/tea/mana I think apurvanandan[m] would appreciate some assistance with the code for the temperature stress test
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| 14:07 | se6ast1an | I have a thermal camera ready to take measurements
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| 14:07 | Bertl | excellent!
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| 14:09 | apurvanandan[m] | Good morning Bertl
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| 15:04 | Amman | Greetings
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| 15:09 | se6ast1an | hi there
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| 15:10 | Amman | Hey. How is it going?
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| 19:36 | apurvanandan[m] | Bertl, Yes the issue was in FIFO logic only :) now the simpler ft601 controller is working, and I am myself amazed how much useless code has been removed. The svf size got halved too.
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| 19:38 | Bertl | great!
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| 19:38 | apurvanandan[m] | Mainly the buffering of data was being used due to wrong handling of clock edges
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| 19:39 | apurvanandan[m] | But unfortunately the previous issue is still there
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| 19:39 | Bertl | can you generate a simulation VCD of the signals invovled for current setup?
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| 19:39 | apurvanandan[m] | I lose values due to fifo getting full
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| 19:40 | apurvanandan[m] | Yes, I sending the VCD in a moment
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| 20:04 | apurvanandan[m] | https://drive.google.com/drive/folders/1Gw3Ei6eRlRSOe8W10eacfuRnK_bJQuQS?usp=sharing
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| 20:04 | apurvanandan[m] | The vcd file and wlf file
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| 20:05 | apurvanandan[m] | https://gist.github.com/apurvanandan1997/ed2d060b068373d4ffae777930ff69ce
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| 20:05 | apurvanandan[m] | The final working code
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| 20:08 | Bertl | why do we have the 60MHz clock now?
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| 20:09 | Bertl | and I do not see the fifo signals in the VCD
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| 20:09 | apurvanandan[m] | They are unnconnected, I didn't remove signals which are useful for future testing
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| 20:09 | apurvanandan[m] | From the testbench
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| 20:10 | apurvanandan[m] | FIFO out directly connected to FT601 data out using a wire
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| 20:11 | Bertl | how about fifo_rd_en and fifo_*emp?
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| 20:12 | Bertl | the FT_WR seems to happen two cycles after the FT_TXE, shouldn't that be one cycle?
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| 20:13 | apurvanandan[m] | That doesn't matter
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| 20:13 | apurvanandan[m] | https://ibb.co/r5DD2Zf
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| 20:13 | Bertl | yes, but you lose a cycle there
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| 20:14 | apurvanandan[m] | How, if we don't enable write txe will be forever 0
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| 20:14 | Bertl | now for the real world test setup, the FIFO is now 1024 words deep?
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| 20:14 | Bertl | and still you lose data?
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| 20:14 | apurvanandan[m] | Yes
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| 20:15 | Bertl | what size are the USB transfers?
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| 20:15 | apurvanandan[m] | I am at same state as two days earlier
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| 20:16 | Bertl | also, the data dump you showed me last time had errors on precisely the same position every time
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| 20:16 | apurvanandan[m] | When I stop data creation on fifo being full, I don't lose data but when I don't I lose 100 words every milion words
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| 20:16 | apurvanandan[m] | Yes that was a issue of clock edge and is solved
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| 20:17 | Bertl | how much did you lose before the fifo depth change?
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| 20:17 | apurvanandan[m] | Approximately samw
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| 20:17 | apurvanandan[m] | same*
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| 20:19 | apurvanandan[m] | Yes one thing I noticed now, when I stop data generation I don't lost any word, but when I stop on fifo full condition I lose approx thousand words every 200Gbits of dataa received
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| 20:20 | apurvanandan[m] | Let me rephrase
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| 20:20 | Bertl | so first, there is a big difference betwenn 100/1mio and 1000/200Gbit
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| 20:21 | apurvanandan[m] | In one case I stop data generation when FIFO gets almost full then no loss
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| 20:21 | Bertl | obvious
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| 20:21 | apurvanandan[m] | When I stop on FIFO full condition, I lose 100 words every 200Gbits
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| 20:22 | apurvanandan[m] | *1000
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| 20:22 | Bertl | this sounds like a bug somewhere
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| 20:22 | apurvanandan[m] | When I don't stop I lost 1000s words per million words
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| 20:22 | Bertl | i.e. fifo full should be sufficient to prevent any loss if you stop data generation
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| 20:23 | apurvanandan[m] | Regarding the two cycle delay after TXE
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| 20:24 | apurvanandan[m] | I have to say that fifo takes one cycle to give new data, but the FT601_wr needs to be high just along with new data
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| 20:24 | Bertl | so one cycle is enough, as I suspected
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| 20:24 | apurvanandan[m] | So a cycle where no change is visible in vcd
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| 20:25 | apurvanandan[m] | That is one second cycle you give data right?
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| 20:25 | Bertl | i.e. set fifo read in one cycle and the write in the next
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| 20:25 | Bertl | will come along with the data
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| 20:25 | Bertl | anyway, you have plenty of other problems, was just making a comment there
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| 20:26 | Bertl | now have you tested 100% throughput with the new setup?
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| 20:26 | apurvanandan[m] | https://ibb.co/r5DD2Zf
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| 20:26 | apurvanandan[m] | I meant the wr_n is perfectly aligned with new data
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| 20:26 | apurvanandan[m] | Yes tested ok
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| 20:27 | Bertl | so, once again, just to recap, 100% throughput, 3.2Gbit works without data loss
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| 20:27 | Bertl | no need to ever stop any data generation, etc
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| 20:27 | apurvanandan[m] | Let me check once more
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| 20:27 | Bertl | FIFO never gets full, etc
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| 20:28 | apurvanandan[m] | Just to be double sure
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| 20:28 | Bertl | yeah, make it triple :)
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| 20:49 | apurvanandan[m] | umm, there is a slight change in simulation waveform
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| 20:51 | apurvanandan[m] | FT601_wr_n is now one cycle before ie txe change on one clock, wr_n on next, data on after wr_n
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| 20:53 | apurvanandan[m] | This is due to the fact that once txe is low then the packet currently out of fifo is not transmitted
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| 22:21 | Bertl | apurvanandan[m]: any news on the double/triple check?
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| 22:22 | apurvanandan[m] | Not working :(
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| 22:23 | Bertl | which means?
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| 22:23 | apurvanandan[m] | FIFO full condition is always required
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| 22:24 | apurvanandan[m] | Otherwise lot of data gets miss
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| 22:24 | Bertl | so what was the 'no dataloss' case you reported?
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| 22:24 | apurvanandan[m] | I am checking for the bug
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| 22:25 | apurvanandan[m] | ie stop writing when FIFO gets full
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| 22:26 | apurvanandan[m] | Just give me an hour or so, to try out things
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| 22:26 | Bertl | okay
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| 22:56 | se6ast1an | off to bed
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| 22:56 | se6ast1an | nn
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| 22:58 | Bertl | sleep well
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| 23:15 | apurvanandan[m] | Bertl, Can I attach a counter that pause the transfer after every 256 words?
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| 23:17 | Bertl | I do not see why not?
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| 23:17 | apurvanandan[m] | Okay
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| 23:20 | Bertl | what's the idea behind this?
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| 23:22 | apurvanandan[m] | To eliminate all cases when fifo gets empty in between of transfer. So I start with around 300 words in fifo and send 256 words and then again wait for fifo to fill upto 300
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| 23:23 | Bertl | okay
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| 23:23 | apurvanandan[m] | Maybe I am wrong, but testing this won't hurt
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