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#apertus IRC Channel Logs

2019/08/08

Timezone: UTC


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Fares
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Nira
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BAndiT1983|away
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BAndiT1983
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04:48
Bertl
off to bed now ... have a good one everyone!
04:48
Bertl
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04:48
apurvanandan[m]
Good night :)
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BAndiT1983|away
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BAndiT1983
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09:28
namibj
I'm sorry I didn't yet write the email as I was told.
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14:00
Bertl_zZ
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14:00
Bertl
morning folks!
14:06
se6ast1an
good day
14:07
se6ast1an
once you got your morning coffee/tea/mana I think apurvanandan[m] would appreciate some assistance with the code for the temperature stress test
14:07
se6ast1an
I have a thermal camera ready to take measurements
14:07
Bertl
excellent!
14:09
apurvanandan[m]
Good morning Bertl
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Amman
Greetings
15:09
se6ast1an
hi there
15:10
Amman
Hey. How is it going?
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intrac
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16:09
Bertl
off for now .. bbs
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Bertl
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BAndiT1983|away
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Bertl_oO
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18:41
BAndiT1983
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19:36
apurvanandan[m]
Bertl, Yes the issue was in FIFO logic only :) now the simpler ft601 controller is working, and I am myself amazed how much useless code has been removed. The svf size got halved too.
19:38
Bertl
great!
19:38
apurvanandan[m]
Mainly the buffering of data was being used due to wrong handling of clock edges
19:39
apurvanandan[m]
But unfortunately the previous issue is still there
19:39
Bertl
can you generate a simulation VCD of the signals invovled for current setup?
19:39
apurvanandan[m]
I lose values due to fifo getting full
19:40
apurvanandan[m]
Yes, I sending the VCD in a moment
19:42
Nira|away
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BAndiT1983|away
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20:04
apurvanandan[m]
https://drive.google.com/drive/folders/1Gw3Ei6eRlRSOe8W10eacfuRnK_bJQuQS?usp=sharing
20:04
apurvanandan[m]
The vcd file and wlf file
20:05
apurvanandan[m]
https://gist.github.com/apurvanandan1997/ed2d060b068373d4ffae777930ff69ce
20:05
apurvanandan[m]
The final working code
20:08
Bertl
why do we have the 60MHz clock now?
20:09
Bertl
and I do not see the fifo signals in the VCD
20:09
apurvanandan[m]
They are unnconnected, I didn't remove signals which are useful for future testing
20:09
apurvanandan[m]
From the testbench
20:10
apurvanandan[m]
FIFO out directly connected to FT601 data out using a wire
20:11
Bertl
how about fifo_rd_en and fifo_*emp?
20:12
Bertl
the FT_WR seems to happen two cycles after the FT_TXE, shouldn't that be one cycle?
20:13
apurvanandan[m]
That doesn't matter
20:13
apurvanandan[m]
https://ibb.co/r5DD2Zf
20:13
Bertl
yes, but you lose a cycle there
20:14
apurvanandan[m]
How, if we don't enable write txe will be forever 0
20:14
Bertl
now for the real world test setup, the FIFO is now 1024 words deep?
20:14
Bertl
and still you lose data?
20:14
apurvanandan[m]
Yes
20:15
Bertl
what size are the USB transfers?
20:15
apurvanandan[m]
I am at same state as two days earlier
20:16
Bertl
also, the data dump you showed me last time had errors on precisely the same position every time
20:16
apurvanandan[m]
When I stop data creation on fifo being full, I don't lose data but when I don't I lose 100 words every milion words
20:16
apurvanandan[m]
Yes that was a issue of clock edge and is solved
20:17
Bertl
how much did you lose before the fifo depth change?
20:17
apurvanandan[m]
Approximately samw
20:17
apurvanandan[m]
same*
20:19
apurvanandan[m]
Yes one thing I noticed now, when I stop data generation I don't lost any word, but when I stop on fifo full condition I lose approx thousand words every 200Gbits of dataa received
20:20
apurvanandan[m]
Let me rephrase
20:20
Bertl
so first, there is a big difference betwenn 100/1mio and 1000/200Gbit
20:21
apurvanandan[m]
In one case I stop data generation when FIFO gets almost full then no loss
20:21
Bertl
obvious
20:21
apurvanandan[m]
When I stop on FIFO full condition, I lose 100 words every 200Gbits
20:22
apurvanandan[m]
*1000
20:22
Bertl
this sounds like a bug somewhere
20:22
apurvanandan[m]
When I don't stop I lost 1000s words per million words
20:22
Bertl
i.e. fifo full should be sufficient to prevent any loss if you stop data generation
20:23
apurvanandan[m]
Regarding the two cycle delay after TXE
20:24
apurvanandan[m]
I have to say that fifo takes one cycle to give new data, but the FT601_wr needs to be high just along with new data
20:24
Bertl
so one cycle is enough, as I suspected
20:24
apurvanandan[m]
So a cycle where no change is visible in vcd
20:25
apurvanandan[m]
That is one second cycle you give data right?
20:25
Bertl
i.e. set fifo read in one cycle and the write in the next
20:25
Bertl
will come along with the data
20:25
Bertl
anyway, you have plenty of other problems, was just making a comment there
20:26
Bertl
now have you tested 100% throughput with the new setup?
20:26
apurvanandan[m]
https://ibb.co/r5DD2Zf
20:26
apurvanandan[m]
I meant the wr_n is perfectly aligned with new data
20:26
apurvanandan[m]
Yes tested ok
20:27
Bertl
so, once again, just to recap, 100% throughput, 3.2Gbit works without data loss
20:27
Bertl
no need to ever stop any data generation, etc
20:27
apurvanandan[m]
Let me check once more
20:27
Bertl
FIFO never gets full, etc
20:28
apurvanandan[m]
Just to be double sure
20:28
Bertl
yeah, make it triple :)
20:49
apurvanandan[m]
umm, there is a slight change in simulation waveform
20:51
apurvanandan[m]
FT601_wr_n is now one cycle before ie txe change on one clock, wr_n on next, data on after wr_n
20:53
apurvanandan[m]
This is due to the fact that once txe is low then the packet currently out of fifo is not transmitted
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BAndiT1983
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illwieckz
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illwieckz
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22:21
Bertl
apurvanandan[m]: any news on the double/triple check?
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illwieckz
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22:22
apurvanandan[m]
Not working :(
22:23
Bertl
which means?
22:23
apurvanandan[m]
FIFO full condition is always required
22:24
apurvanandan[m]
Otherwise lot of data gets miss
22:24
Bertl
so what was the 'no dataloss' case you reported?
22:24
apurvanandan[m]
I am checking for the bug
22:25
apurvanandan[m]
ie stop writing when FIFO gets full
22:26
apurvanandan[m]
Just give me an hour or so, to try out things
22:26
Bertl
okay
22:56
se6ast1an
off to bed
22:56
se6ast1an
nn
22:58
Bertl
sleep well
23:15
apurvanandan[m]
Bertl, Can I attach a counter that pause the transfer after every 256 words?
23:17
Bertl
I do not see why not?
23:17
apurvanandan[m]
Okay
23:20
Bertl
what's the idea behind this?
23:22
apurvanandan[m]
To eliminate all cases when fifo gets empty in between of transfer. So I start with around 300 words in fifo and send 256 words and then again wait for fifo to fill upto 300
23:23
Bertl
okay
23:23
apurvanandan[m]
Maybe I am wrong, but testing this won't hurt