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#apertus IRC Channel Logs

2017/08/08

Timezone: UTC


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Bertl_oO
off to bed now .. have a good one everyone!
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09:32
Bertl
morning folks!
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Bertl
off for now ... bbl
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Bertl
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19:10
felix_
Bertl_oO, mithro: hmm, we might get away without an extra fpga for the axiom sdi output board and that would fit a 3g sdi output on a sngle axiom connector. have a look at the LMH0340. that would also fit into my planned design for litesdi without problems
19:11
felix_
is currently looking at the different sdi chips from different vendors
19:12
Bertl_oO
sounds good, and yes, I already considered the LMH0340
19:16
felix_
it's 3g sdi only (2x 3g still possible), but much smaller and cheaper than the option with an extra fpga. and we won't loose much flexibility
19:17
Bertl_oO
correct, good thinking!
19:27
Kjetil
can you get a correct/sufficient performance output clock from the main fpga?
19:27
Kjetil
s/main fpga/main fpga board/
19:30
Kjetil
(figure 16 in the datasheet)
19:32
Bertl_oO
probably, but still if we need a clock synthesizer, it's a lot simpler than with an FPGA
19:33
Kjetil
if you are going to support ref-input you probably need some kind of tunable clock synthesizer regardless
19:33
felix_
have to look, but even if we need an external clock generator (which is something i suspect), it's still cheaper and simpler
19:34
Kjetil
I guess you have the ability to feed the clock from the add-on board to the main fpga?
19:34
felix_
yep
19:46
Kjetil
hm.. I guess you need to do 2x3G-SDI Level B to support 4K@24hz then
21:57
felix_
seems that semtech is the only company that has 6g sdi chips with publically available datasheet. /me can't think of any super secret stuff in the pdf files. i mean the "magic" is in the chip, not in the datasheet
22:14
Bertl_oO
tell that to Marvell and friends ...
22:15
Bertl_oO
SATA Phy, top secret!!!
22:32
felix_
well, the datasheets for the 3g sdi stuff are more or less all available (except for the semtech chips where the spec isn't final yet)