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#apertus IRC Channel Logs

2021/06/08

Timezone: UTC


01:22
intrac
joined the channel
03:59
Bertl_oO
off to bed now ... have a good one everyone!
03:59
Bertl_oO
changed nick to: Bertl_zZ
08:03
se6astian
good morning
08:09
BAndiT1983
hi
09:40
Tr3n4rT
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10:01
Tr3n4rT
left the channel
11:30
Bertl_zZ
changed nick to: Bertl
11:30
Bertl
morning folks!
12:04
se6astian
good day
12:53
Spirit532
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13:01
Spirit532
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15:47
balrog
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16:28
anuejn
yay, the naps testsuite is green again and we dont need tooo horrible hacks for that anymore :)
16:29
se6astian
hurray!
16:59
vup
yay
18:06
tpw_rules
anuejn: first pr is done! hopefully it is good
18:24
anuejn
tpw_rules: I have to admit that I dont really understand the problem with using the connectors
18:24
anuejn
since you are creating one DiffPairs per lane anyways
18:25
vup
(I also left some notes)
18:26
tpw_rules
vup: is your name `rroohhh` on github?
18:26
vup
yeah
18:27
tpw_rules
ok. i chose not to use the connectors because it would have been an additional table. i just wasn't sure of a good way to represent the data
18:28
tpw_rules
also i did not use SPIResource because the micro r2 platform did not use I2CResource. i forgot to ask but both should probably be changed to use the corresponding Resource
18:28
anuejn
yup sounds good
18:30
vup
tpw_rules: not really, you could use the `JX{1,2}_0:{num}` syntax to avoid a seperate table, no?
18:30
vup
micro r2 should probably use I2CResource :)
18:30
tpw_rules
i will change both to use the Resource
18:30
vup
great
18:30
tpw_rules
i could, i did not know that syntax existed. but then the table would be really wide
18:32
vup
If you want to avoid having the table very wide, you could just have a table of tuples, with (connector number, number on connector) and generate the full string in the for loop
18:33
vup
(or a table with "1:3 2:4 1:123 ...")
18:33
tpw_rules
ok, i prefer a tall table. would you object to having the table as a module constant?
18:33
vup
nope that seems fine
18:35
tpw_rules
ah, i remember another reason i did not use SPIResource: i don't think it's possible to represent that chip select is active high
18:40
tpw_rules
also, is it possible to simply swap the P and N pins for lane 18 or will that upset the FPGA pin layout planner?
18:45
vup
tpw_rules: Ahh, that is indeed a problem, do you want to open a nmigen-boards issue about that?
18:47
vup
simply swapping the pins does not work unfortunately, you will get vivado yelling at you by doing that :)
18:47
tpw_rules
i can do that
18:47
tpw_rules
and okay, that's kind of what i expected. i guess which pins are P and which are N is fixed into the silicon
18:47
vup
yep
18:49
tpw_rules
is it okay if i force push the changes or would you prefer a new commit
18:51
vup
force pushing is fine
18:59
Bertl
off for now ... bbl
18:59
Bertl
changed nick to: Bertl_oO
19:02
tpw_rules
okay the new version is up
19:14
tpw_rules
vup: actually, let me change the spi pin names to use the SPIResource ones instead of the sensor ones, that will probably make more sense in the long run
19:14
vup
yeah, makes sense
19:15
tpw_rules
also i just saw your comment, let me confirm the direction too