| 00:14 | Bertl_oO | off to bed now ... have a good one everyone!
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| 08:24 | Bertl | morning folks!
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| 10:42 | danieel | Bertl / se6astian - do you remember when a JP4 was first seen with the elpher hardware? (or any prior art on compressed bayer?)
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| 10:42 | danieel | *elphel
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| 10:43 | Bertl | nope, why?
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| 10:44 | danieel | trolling from a company who thinks invented the digital camera
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| 10:56 | se6astian | should be easy to find such dates in the elphel wiki history
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| 11:00 | danieel | says 2010, so better to rely on cineform raw, that dates back to 2006
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| 12:04 | Bertl | off for now ... bbl
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| 12:18 | LordVan | hi
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| 12:18 | LordVan | how was maker faire?
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| 12:26 | RexOrCine | Pretty good.
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| 13:36 | nmdis1999 | Bertl, I have mailed the ssh-key :)
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| 13:40 | se6astian | thanks, we received
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| 16:10 | ArunM | Hello Bertl_oO
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| 16:12 | ArunM | he checks logs, just droping link for the sensor emulator design document
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| 16:12 | ArunM | it has no specific format and casually explains the implemntation
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| 16:12 | ArunM | https://docs.google.com/document/d/1JIUxDIvjf85m0RCa2SDYGKCRv28YbKdpGoXXqD9tii8/edit?usp=sharing
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| 16:14 | ArunM | I've already started coding to test few things during designing
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| 16:15 | ArunM | but i'll wait for your review b4 going further
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| 16:36 | BAndiT1983 | hey TofuLynx, how is it going?
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| 18:34 | Bertl_oO | ArunM: looks good (just briefly checked it right now) here some points which need to be considered
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| 18:35 | ArunM | listening :-)
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| 18:35 | Bertl_oO | - the LVDS channels are not synchronized, they have a delay
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| 18:35 | Bertl_oO | i.e. they seem to be synchronized to the clock, but they all have a specific offset
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| 18:35 | Bertl_oO | (this is most likely to reduce the switching effects)
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| 18:36 | Bertl_oO | - some registers seem to have 'read only' bits and some registers are not well documented
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| 18:37 | Bertl_oO | so it would be good to have some masking mechanism there
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| 18:38 | Bertl_oO | - the clocks have to be in a specific relation to eachother
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| 18:38 | Bertl_oO | more detail on that later
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| 18:39 | ArunM | didn't found any specific information about it in the datasheet itself any other place to look?
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| 18:39 | ArunM | about clocks
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| 18:39 | Bertl_oO | there is some information in the datasheet but it is strangley worded
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| 18:40 | ArunM | yes i found it like that too ;-)
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| 18:40 | ArunM | okay I'll take care of the rest
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| 18:41 | Bertl_oO | great!
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| 18:41 | Bertl_oO | it might be cool to consider some kind of cosimulation and verification
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| 18:42 | Bertl_oO | i.e. at some point have the sensor simulation running side by side with a real sensor and check where we hit differences
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| 18:45 | ArunM | cool indeed but how is it possible?
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| 18:45 | ArunM | you are going to do that right!! i can only write test benches from here
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| 18:46 | Bertl_oO | well, if we can fit the simulation into the zynq together with the normal image pipeline, we just need to write a little HDL to compare the output
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| 18:46 | Bertl_oO | of course, this will only work for test image data
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| 18:47 | ArunM | nice, this project got more interesting
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| 23:25 | Bertl_oO | off to bed now ... have a good one everyone!
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| 23:47 | TofuLynx | Off to bed too... Good night everyone!
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