#apertus IRC Channel Logs

yes

apurvanandan[m] is the beta_e free ?

off to bed now ... have a good one everyone!

morning folks!

Hi, can someone please explain clks generated and used in axiom beta? I found several PLL output 250MHZ and 148.5MHZ and in scripts there is four other clks 100,10,1,125MHZ

there are four*

the AXIOM Beta doesn't add one there either, because of the limited IO pins

the main source for clocking on the PL are the FCLKs which are special PS derived and configured clocks routed into the fabric

typically those clocks are fed into a PLL or MMCM which then generates the required clocks for the fabric

fclk3 is currently unused and left at 124.999 MHz

and FCLKs are four, how many PLL/MMCM available in ZYNQ?

currently there are two PLL/MMCMs active in cmv_hdmi code

and the other one which generates all the HDMI related clocks

yeah, that is basically part of the CMV PLL construct

and lvds_pll derives the clocks from the output of the CMV12k

I know it is only used in vivado for synthesizing and implementation, but when I try to set the FCLKs from ps side, it only change to specific values, I couldn't tune it

so you need to run some PS code to modify them and yes, they do not allow many different settings

e.g. 50MHz is fine, but 60MHz yields 59.52381MHz

see 7 series PLL documentation for details

ok I will, so I want to generate 200MHZ to 215MHZ clk, is it better to use FCLK or PLL?

ok I will read more about it

so its geared up by a pll for actual use

I will read about it and get back if I have any more questions thank you, actually I was wondering how my output will be connecting to the lvds? Now i output 16bits per cycle, how will it transfer to the usb module?

but basically there will be a transfer over 6 LVDS pairs from Zynq to MachXO2 on the USB plugin

excellent!

Ok great you are here, I will do something and talk to you after 15 mins ok?

I think there is some room for improvement

also note that it would be really great to have some information on the project page which explains what it is actually about, best with some diagrams

Hi apurvanandan[m]

Can you explain to me please how data is transferred between ZYNQ and MachXO2?

So Fares it is a source synchronous setup between them

There are 6 DC coupled LVDS lanes between them for data transfer

The aim is to send the 48 bit pixel data read directly from RAM to the FTDI chip on USB module which in turn sends it to the connected PC

ie 600 Mbps

Once everything is complete I should achieve a bandwidth of 3.2Gbps

Extending to all lanes is left to do atm

I haven't decided that yet, but atm I am sending 8 bits words with 8b/10b encoding over 10:1 Serdes

I need to figure out how to gear with 48 bit words

When I use all lanes ie 5 lanes for data, I will need to send 40 bit words

48 can be split into 3x16 or lj92 3x16 can be concatenated into 48

Yup, can be sent easily,

Fares_: why 3x16?

Yes Fares

okay, let me rephrase, why 48 for RGGB?

Frame data I mean

but we are talking lj92 output, no?

Or per several cycles* but 40bits is the amount of data for 5 lanes, correct?

at the moment, yes

I wouldn't try to match the USB transfer speed yet

basically we aim at 100MBaud with 32bit output via the FTDI

the connection between Zynq and MachXO2 needs to provide at least this bandwidth

something like this, yes

I thought that was your estimation :)

Fares_: but anyway, for now, we aim at 1 USB3 module which transfers the data, there is no point in producing more data than we can get out

aSobhy: which link?

can you have a look to confirm :)

Yes that is correct :) I estimated 82MHz from the 40bits, but I mean why not 20bits at 164 for example :))

at some point it will have to go over 5 or 6 LVDS pairs at 600+ MHz, that's all

no in order to enable ZYNQ to make the work its doing before I run my code on it

the i2c_minimal is what you want to incorporate in your Zynq design so that everything (basically I2C and clocks) work as required to program and control the MachXO2s

Bertl: that assuming something faster than usb3.0, but for now I am writing efficient module to split 64 bits from axihp_reader to two 24bits data, should I write something more for the lj92 output as well? Lj92 will output 16bits in most cycles.

if you want to help apurvanandan[m] with the output gearing that's fine (but I'd say 16bit is fine, probably needs a fifo anyway before it goes over LVDS)

Ok great! I will complete few things including PLL and more documentations, then I will talk with apurvanandan[m] to check if help is needed in the output gearing

you're welcome!

I will be thankful for any help Fares

execellent!

remote beta programming?

Scroll up on beta irc channel

Bertl, you suggested me to make 1024 word deep fifo

The calc behind it was 8 Kb /32 =256 x 4 =1024 right?

nope

the FT60x manual talks about 1024 byte packets

we submit 32bit words to the FT60x

note: It was for 4KB buffer size

note: we still need to check that via wireshark

ahh, wireshark will be good for debugging

and using almost empty/full at 256/768 words respectively should give good debug information

yeah, I don't think the packet size changes when you change the FT FIFO depth

ahh, Got it

we don't know what the FTDI will do with its buffer

Okay fine

Just a little confusion

So Bertl, do we need to use falling edge FFs

do you plan to sample the signal while it is changing to add some randomness to the design? :)

apurvanandan[m]: I will be at the office tomorrow and Bertl prepared me to run some temperature measurements with the usb3 module and you then

off to bed now

apurvanandan[m]: you might want to prepare some MachXO2/FTDI designs which produce a lot of heat :)

hot! not cool! :)