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#apertus IRC Channel Logs

2019/08/07

Timezone: UTC


01:00
aSobhy
yes
01:01
aSobhy
I'm finishing the jtagf and generate the bitstream files
01:01
aSobhy
apurvanandan[m] is the beta_e free ?
01:01
apurvanandan[m]
Wait aSobhy Bertl is busy with it
05:18
Bertl
off to bed now ... have a good one everyone!
05:18
Bertl
changed nick to: Bertl_zZ
05:33
BAndiT1983|away
changed nick to: BAndiT1983
05:44
futarisIRCcloud
joined the channel
06:55
BAndiT1983
changed nick to: BAndiT1983|away
08:55
danieel
left the channel
08:56
danieel
joined the channel
12:51
Bertl_zZ
changed nick to: Bertl
12:51
Bertl
morning folks!
15:08
Fares
joined the channel
15:11
Fares
Hi, can someone please explain clks generated and used in axiom beta? I found several PLL output 250MHZ and 148.5MHZ and in scripts there is four other clks 100,10,1,125MHZ
15:11
Fares
are they all generated and used? and can I generate another clk frequency?
15:13
Fares
there are four*
15:18
Bertl
the MicroZed doesn't feature a crystal or oscillator on the PL side
15:18
Bertl
the AXIOM Beta doesn't add one there either, because of the limited IO pins
15:19
Bertl
thus all frequencies are derived from the PS clock (33.33MHz oscillator) in one or the other way
15:19
Bertl
the main source for clocking on the PL are the FCLKs which are special PS derived and configured clocks routed into the fabric
15:20
Bertl
there are four of them and they are used for different purposes throughout the Beta
15:20
Bertl
typically those clocks are fed into a PLL or MMCM which then generates the required clocks for the fabric
15:22
Bertl
just yesterday we went through the future clocking setup and kind of decided to set fclk0 to 50MHz (main clock for fabric) and fclk1/2 to 10MHz (shared clock for routing fabrics)
15:23
Bertl
fclk3 is currently unused and left at 124.999 MHz
15:24
Fares
okay so the FCLKs are constants and they are partially used in the PL, and the PLL/MMCM are the ones that we used when needing specific frequency?
15:24
Fares
and FCLKs are four, how many PLL/MMCM available in ZYNQ?
15:25
Bertl
the fclks can be configured on the PS, but we consider them constant for the PL unless there is a good reason to change that
15:25
Bertl
currently there are two PLL/MMCMs active in cmv_hdmi code
15:26
Bertl
one which generates all the clocks related to the CMV12k
15:26
Bertl
and the other one which generates all the HDMI related clocks
15:26
Fares
and one for lvds?
15:26
Bertl
yeah, that is basically part of the CMV PLL construct
15:27
Bertl
i.e. cmv_pll generates the input for CMV12k
15:27
Bertl
and lvds_pll derives the clocks from the output of the CMV12k
15:29
Fares
ok great, also is PLL is more configurable than FCLKs? since FCLKs can take only specific values because of 33.33MHZ - when I tried to change them in vivado -
15:31
Fares
I know it is only used in vivado for synthesizing and implementation, but when I try to set the FCLKs from ps side, it only change to specific values, I couldn't tune it
15:33
Bertl
well, you cannot change the FCLKs from the PL side
15:33
Bertl
so you need to run some PS code to modify them and yes, they do not allow many different settings
15:35
Fares
so is PLL will allow more settings or the same?
15:35
Bertl
e.g. 50MHz is fine, but 60MHz yields 59.52381MHz
15:35
Bertl
the PLL/MMCM is part of the fabric, and can be extensively configured
15:35
Bertl
see 7 series PLL documentation for details
15:36
Bertl
UG472
15:37
Fares
ok I will, so I want to generate 200MHZ to 215MHZ clk, is it better to use FCLK or PLL?
15:38
Bertl
probably PLL
15:40
Fares
ok I will read more about it
15:44
Bertl
let me know if you have specific questions ...
15:45
Fares_
joined the channel
15:45
Fares__
joined the channel
15:46
Fares
left the channel
15:49
danieel
Bertl: the 50M fabric clock is really what the logic runs at? is that for power consumption, or too many levels of logic? (or that fabric is nothing related to cmv or hdmi portions?)
15:49
Fares_
left the channel
15:49
Bertl
it is just a clock the PS can generate well, it isn't used 'by the fabric'
15:50
danieel
so its geared up by a pll for actual use
15:50
Bertl
PLL/MMCM, yes
15:51
Fares__
I will read about it and get back if I have any more questions thank you, actually I was wondering how my output will be connecting to the lvds? Now i output 16bits per cycle, how will it transfer to the usb module?
15:51
Bertl
that's something apurvanandan[m] is working on
15:52
Bertl
but basically there will be a transfer over 6 LVDS pairs from Zynq to MachXO2 on the USB plugin
15:55
Fares__
The gearing work, ok I will have a chat with apurvanandan[m] to see exactly how it will integrate with his work
15:55
Bertl
excellent!
15:55
apurvanandan[m]
And I am most of time available for chat here
15:58
Fares__
Ok great you are here, I will do something and talk to you after 15 mins ok?
15:58
apurvanandan[m]
No problem
16:02
Fares__
left the channel
16:06
se6ast1an
hi apurvanandan[m], please take a look at the wiki page you created
16:06
se6ast1an
I think there is some room for improvement
16:06
se6ast1an
take https://wiki.apertus.org/index.php/JPEG_1992_lossless_encoder_core as reference
16:10
Bertl
also note that it would be really great to have some information on the project page which explains what it is actually about, best with some diagrams
16:14
apurvanandan[m]
Hi se6ast1an , Actually I haven't started working on it till now. You won't have any complaints once I finish that.
16:16
Fares
joined the channel
16:16
se6ast1an
Great!
16:17
Fares
Hi apurvanandan[m]
16:18
apurvanandan[m]
Hi
16:20
Fares_
joined the channel
16:20
Fares
left the channel
16:21
Fares_
Can you explain to me please how data is transferred between ZYNQ and MachXO2?
16:22
RexOrMatrix[m]
Fares: Nice wiki page lad.
16:25
apurvanandan[m]
So Fares it is a source synchronous setup between them
16:25
Fares_
Thank you, I am still working on it
16:25
apurvanandan[m]
There are 6 DC coupled LVDS lanes between them for data transfer
16:26
apurvanandan[m]
I use 1 lane for clock and other 5 for data transfer
16:27
apurvanandan[m]
The aim is to send the 48 bit pixel data read directly from RAM to the FTDI chip on USB module which in turn sends it to the connected PC
16:28
apurvanandan[m]
Current status is I am somewhat able to transfer data using 2 LVDS lanes at 300MHz DDR
16:28
apurvanandan[m]
ie 600 Mbps
16:28
Fares_
600Mbps per lane correct?
16:28
apurvanandan[m]
Once everything is complete I should achieve a bandwidth of 3.2Gbps
16:29
apurvanandan[m]
I am still working with 1 lane only, other is for clock
16:29
apurvanandan[m]
Extending to all lanes is left to do atm
16:29
Fares_
Ok great I understand now, so how 16 or 32 or 48 bits serialization happens?
16:30
apurvanandan[m]
I haven't decided that yet, but atm I am sending 8 bits words with 8b/10b encoding over 10:1 Serdes
16:31
apurvanandan[m]
in one lane
16:31
apurvanandan[m]
I need to figure out how to gear with 48 bit words
16:32
Fares_
48 for rggb correct? But for lj92 it would be 16.
16:32
apurvanandan[m]
When I use all lanes ie 5 lanes for data, I will need to send 40 bit words
16:32
apurvanandan[m]
Yes for rggb its 48
16:32
Fares_
48 can be split into 3x16 or lj92 3x16 can be concatenated into 48
16:32
apurvanandan[m]
So I need to gear the 48 bits into 40 bits
16:33
apurvanandan[m]
Yup, can be sent easily,
16:34
apurvanandan[m]
On software end ie on the PC we can receive only 32 bit words for max bandwidth, so some gearing on PC also for converting back to 48
16:35
Bertl
Fares_: why 3x16?
16:35
Fares_
I assume gearing in the pc is quite easy, specially if SIMD instructions are used. But gearing from 48 to 40bits will happen in the zynq correct?
16:36
apurvanandan[m]
Yes Fares
16:38
Fares_
Bertl: it is only example of how we can split or concatenate the data from ram or lj92
16:38
Bertl
okay, let me rephrase, why 48 for RGGB?
16:39
Fares_
Data is stored in memory in 64bits chunks, every chunk has RGGB data in 48bits in the high order bits, correct?
16:40
Fares_
Frame data I mean
16:40
Bertl
correct
16:40
Bertl
but we are talking lj92 output, no?
16:41
Fares_
Correct, but apurvanandan[m] calculations were based on raw data, but ideally lj92 should output 40bits per cycle, correct apurvanandan[m] ?
16:42
Fares_
Or per several cycles* but 40bits is the amount of data for 5 lanes, correct?
16:42
apurvanandan[m]
Yes you are right
16:43
Bertl
at the moment, yes
16:43
Fares_
In what clk frequency? Or clk frequency is irrelevant for those 40bits?
16:44
Bertl
I wouldn't try to match the USB transfer speed yet
16:44
apurvanandan[m]
40 bits at 300Mhz to 358 MHz
16:45
Bertl
basically we aim at 100MBaud with 32bit output via the FTDI
16:45
Bertl
(which is the limit of the FTDI parallel input)
16:46
Bertl
the connection between Zynq and MachXO2 needs to provide at least this bandwidth
16:50
Fares_
Aha I understand, so around ((3.2/5lanes)/2ddr)MHz for the lvds â and for the lj92 40bits, less than 82MHz clk?
16:51
Bertl
something like this, yes
16:53
Fares_
May I ask why 40bits at around 82MHz? - from the zynq side
16:54
Bertl
I thought that was your estimation :)
16:55
aSobhy
Bertl I have added i2c from the link you gave before and added the signal in ps7, is that fine ?
16:55
Bertl
Fares_: but anyway, for now, we aim at 1 USB3 module which transfers the data, there is no point in producing more data than we can get out
16:55
Bertl
Fares_: the next step will be to use two USB3 modules and double the bandwidth
16:56
Bertl
aSobhy: which link?
16:56
aSobhy
icsp._test http://vserver.13thfloor.at/Stuff/AXIOM/BETA/icsp_test/
16:56
aSobhy
can you have a look to confirm :)
16:57
Bertl
you mean: http://vserver.13thfloor.at/Stuff/AXIOM/BETA/i2c_minimal/ ?
16:57
Fares_
Yes that is correct :) I estimated 82MHz from the 40bits, but I mean why not 20bits at 164 for example :))
16:57
Bertl
Fares_: ah, that's fine as well
16:58
Bertl
at some point it will have to go over 5 or 6 LVDS pairs at 600+ MHz, that's all
16:59
Bertl
as I said, do not bother too much with the actual word with or data rate just keep the total amount of output bandwidth in mind
17:00
aSobhy
no in order to enable ZYNQ to make the work its doing before I run my code on it
17:00
aSobhy
to check the gpio pins etc
17:01
Bertl
the i2c_minimal is what you want to incorporate in your Zynq design so that everything (basically I2C and clocks) work as required to program and control the MachXO2s
17:03
aSobhy
ok I have to remove 1 of them :) its easy
17:04
Fares_
Bertl: that assuming something faster than usb3.0, but for now I am writing efficient module to split 64 bits from axihp_reader to two 24bits data, should I write something more for the lj92 output as well? Lj92 will output 16bits in most cycles.
17:04
Fares_
The total bandwidth is within the limits
17:06
Bertl
if you want to help apurvanandan[m] with the output gearing that's fine (but I'd say 16bit is fine, probably needs a fifo anyway before it goes over LVDS)
17:06
Bertl
just make sure that your code integration as well as documentation doesn't suffer :)
17:10
Fares_
Ok great! I will complete few things including PLL and more documentations, then I will talk with apurvanandan[m] to check if help is needed in the output gearing
17:11
Fares_
Thank you very much apurvanandan[m] and Bertl for your time
17:11
Bertl
you're welcome!
17:14
BAndiT1983|away
changed nick to: BAndiT1983
17:16
apurvanandan[m]
I will be thankful for any help Fares
17:22
Fares_
It would be my pleasure, I will finish few things and will contact you apurvanandan[m]
17:22
apurvanandan[m]
execellent!
17:23
aSobhy
apurvanandan[m]: where are the commands :P
17:23
apurvanandan[m]
remote beta programming?
17:24
aSobhy
yes last night session
17:24
apurvanandan[m]
Scroll up on beta irc channel
17:25
apurvanandan[m]
There are tons of screenshot
17:27
apurvanandan[m]
Bertl, you suggested me to make 1024 word deep fifo
17:28
Bertl
yup?
17:28
apurvanandan[m]
The calc behind it was 8 Kb /32 =256 x 4 =1024 right?
17:29
apurvanandan[m]
just to confirm once
17:29
Bertl
nope
17:29
apurvanandan[m]
8KB buffer size
17:29
Bertl
the FT60x manual talks about 1024 byte packets
17:29
Fares_
left the channel
17:29
Bertl
we submit 32bit words to the FT60x
17:30
Bertl
so I assume that they get sent in one packet which means 256 words (of 32 bit) per packet
17:30
apurvanandan[m]
note: It was for 4KB buffer size
17:30
apurvanandan[m]
And in 1 IN channel we have 8KB buffer
17:30
Bertl
note: we still need to check that via wireshark
17:31
Bertl
(which you might do as a first step on 100% transfers)
17:31
apurvanandan[m]
ahh, wireshark will be good for debugging
17:31
Bertl
then from 256 word packets and the requirement to keep two of them, we concluded that a 1024 word FIFO should be more than enough
17:32
Bertl
and using almost empty/full at 256/768 words respectively should give good debug information
17:32
apurvanandan[m]
That was for fifo size 4KB
17:33
Bertl
yeah, I don't think the packet size changes when you change the FT FIFO depth
17:33
apurvanandan[m]
But we have fifo size of 8KB in 1 IN channel only
17:33
apurvanandan[m]
ahh, Got it
17:35
apurvanandan[m]
Then also it takes 1 KB now from 8KB buffer right?
17:36
Bertl
we don't know what the FTDI will do with its buffer
17:36
Bertl
but that's fine, we do not care that much
17:37
apurvanandan[m]
Okay fine
18:24
apurvanandan[m]
https://ibb.co/r5DD2Zf
18:24
apurvanandan[m]
Just a little confusion
18:24
apurvanandan[m]
In this figure we see all signals change state at falling edges
18:24
apurvanandan[m]
So Bertl, do we need to use falling edge FFs
18:27
Bertl
hmm?
18:27
Bertl
do you plan to sample the signal while it is changing to add some randomness to the design? :)
18:30
apurvanandan[m]
I am a fool , sorry
19:46
BAndiT1983
changed nick to: BAndiT1983|away
20:03
Nira|away
changed nick to: Nira
21:31
Fares
joined the channel
21:35
Fares
left the channel
22:31
se6ast1an
apurvanandan[m]: I will be at the office tomorrow and Bertl prepared me to run some temperature measurements with the usb3 module and you then
22:31
se6ast1an
I will let you know when I am there
22:31
se6ast1an
off to bed now
22:31
se6ast1an
good night
22:32
Bertl
apurvanandan[m]: you might want to prepare some MachXO2/FTDI designs which produce a lot of heat :)
23:55
apurvanandan[m]
Okay cool
23:55
Bertl
hot! not cool! :)
23:57
apurvanandan[m]
XD lol
00:57
Fares
joined the channel