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#apertus IRC Channel Logs

2019/05/07

Timezone: UTC


00:10
Spirit532
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05:32
BAndiT1983|away
changed nick to: BAndiT1983
06:08
Y_G
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06:31
siddhantsahu
Hey Bertl_zZ se6astian|away BAndiT1983 I didn't make through for this year GSoC, never mind but I plan to contribute to OpenCine project
06:37
Y_G
Hi BAndiT1983 ,would our daily/weekly updates reporting happen in the irc channel itself?
06:37
Y_G
I have seen people using trello board for the same previous year,should I follow the same ?
06:43
mrohit[m]
Congratulations to all of the GSOC participants!
06:43
mrohit[m]
Couldn't make it through this year...but would like to stay with the org and contribute
06:44
mrohit[m]
If you don't mind..can everyone share their proposals.. because previously many students didn't share it publicly
06:47
BAndiT1983
changed nick to: BAndiT1983|away
07:05
_florent__
Bertl_zZ: this wednesday. Next week if fine for me too.
07:20
Bertl_zZ
changed nick to: Bertl
07:21
Bertl
morning folks!
07:22
Bertl
siddhantsahu, mrohit[m]: you are very welcome to stay with us and continue contributing!
07:25
Bertl
felix_:, _florent__, apurvanandan[m], aSobhy|away: I would suggest we do a short discussion/brain storming today in the afternoon then (at least 4/5 seem to have time) and a longer one early next week
07:26
Bertl
how about 14:00 CEST ?
07:42
_florent__
Bertl: that's fine for me
07:44
se6astian|away
changed nick to: se6astian
07:47
se6astian
last year we did a weekly general team/gsoc IRC meeting (those were on Mondays IIRC) to give everyone a chance to present development progress, ask questions and see what the others are up to
07:47
se6astian
we should consider resuming these again soon
08:52
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09:03
Dev__
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09:08
Dev__
Y_G : Trello is a nice way to set up small goals . It has nice interface also , I think you should go for it
09:10
Dev__
Hi Bandit1983 : i am also free for discussion for T763 , please let us know when u will be free .
09:11
Y_G
mrohit[m] : here's my proposal "https://drive.google.com/open?id=1DbKwsqq8JLWx1T4mq0qgSPxMlEKj0iI8RhPu8tlSUmI"
09:12
Y_G
Dev__ ,yes I had a look there,If BAndiT1983 approves I would be using that only
09:13
Y_G
Dev__ which college btw ?
09:14
Dev__
Army institute of technology , pune. , yours??
09:15
Y_G
Nice,I am from Manipal Jaipur
09:17
Dev__
Don't u have exams in next phase yash
09:18
Dev__
University exams*
09:18
Y_G
Final year undergrad ,So I need to only do an internship
09:18
Y_G
Which I succesfully completed yesterday :)
09:19
Y_G
I do need to present my work at the college though
09:19
Dev__
Nice !!
09:21
Dev__
Work of your internship or gsoc , its a nice and rare rule btw
09:24
Y_G
Work of internship,Gsoc I have to start
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10:42
Bertl
Spirit532: problem with the IRC client?
10:42
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10:45
mrohit[m]
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10:51
apurvanandan[m]
Yeah Bertl , Today ( 7 May ) 14:00 CEST (18:30 IST) would be fine for me.
10:51
Bertl
perfect, see you all in a little more than an hour then
10:52
Bertl
off for now ... bbs
10:52
Bertl
changed nick to: Bertl_oO
11:04
Y_G
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11:59
Bertl_oO
changed nick to: Bertl
12:00
Bertl
_florent__, felix_, apurvanandan[m], aSobhy|away: let's begin with a quick introduction
12:02
Bertl
_florent__ is currently working on the software side of a SATA solution (among other) suitable for the AXIOM plugin slots
12:03
Bertl
felix_ is currently working on the SDI plugin module (hardware prototype already done, software still in the works)
12:04
felix_
yep
12:04
Bertl
both projects are based on Artix 7 FPGA on the plugin modules
12:05
Bertl
apurvanandan[m] will be working on the USB 3.0 plugin module during GSoC 2019
12:05
Bertl
and aSobhy|away (who will probably join next time) will be working on the packet protocol between Zynq and routing fabrics in the AXIOM Beta
12:06
Bertl
both GSoC projects are based on data transfer between the Xilinx Zynq and Lattice Mach XO2
12:07
Bertl
and I'll be mentoring both of them during GSoC 2019
12:08
Bertl
if anybody wants to add anything here to the introduction, please go ahead ...
12:11
Bertl
okay, so the basic challenge all those projects are trying to solve (among others) is: how to get data as fast and as reliable as possible from one device to the other
12:13
Bertl
on the lowest level, there is a number of signalling standards which can be used to transfer (usually serial) data between two points
12:14
felix_
the data transfer between the zynq and the machxo2 on one of the camera boards is a bit different from the other modules though; the other modules basically need a big video data pipe, while the former needs bidirectional (but slower) data transfers
12:15
Bertl
correct, but as we aim for low latency there, we also need high data rates (at least at times)
12:15
Bertl
so the most prominent today are LVDS (and the low voltage derivatives) and CML (current mode logic)
12:15
Bertl
more details on those can be found here:
12:15
Bertl
https://en.wikipedia.org/wiki/Low-voltage_differential_signaling
12:16
Bertl
https://en.wikipedia.org/wiki/Current-mode_logic
12:17
Bertl
note that both of them are differential signalling standards and the hardware in all cases is optimized for differential connections
12:19
Bertl
T731 (packet protocol) has 1 and 2 differential pairs available for data transfer
12:19
Bertl
T885 (USB 3.0) has 6 differential pairs available for data transfer
12:20
Bertl
both the SDI and SATA plugins get up to 12 pairs
12:22
Bertl
one approach for high speed serial data transfer is to use one pair for a separate clock signal
12:23
Bertl
this is for example done in HDMI where one of the four high speed serial connections is used to transmit a reference clock
12:24
Bertl
other protocols like for example SATA and DP embed the clock into the data stream and regenerate the clock signal at the receiver
12:26
Bertl
with enough connections (differential pairs) available, the separate clock is probably a rather appealing solution but when the number of connections goes down an embeded clock signal becomes more and more interesting
12:27
Bertl
another option here is to use some kind of low speed side channel to transfer a low speed clock which is in some way related to the actual data clock
12:27
Bertl
usually PLLs are available in modern FPGAs (and they certainly are in Artix 7 and Mach XO2)
12:28
Bertl
so those can be used to regenerate the high speed clock required to serialize and deserialize data
12:28
Bertl
please do not hesitate to add information when you consider it relevant
12:28
illwieckz_
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12:29
_florent__
hi all
12:29
Bertl
(doesn't need to be a monologue :)
12:29
apurvanandan[m]
Hi
12:29
_florent__
thanks Bertl for the explanation, i think it will help the student understand high speed serial links
12:30
Bertl
no problem, that's the idea
12:30
apurvanandan[m]
Does the USB module has oscillator on it?
12:30
Bertl
yes, it has, connected to the FTDI
12:32
Bertl
so, on the next layer, there are different options for encoding the data to make it better suitable for serial transfer
12:32
apurvanandan[m]
ok, and a doubt , You mean to get the PLL in phase with data stream?
12:32
Bertl
there are several options to synchronize a PLL with the data
12:33
Bertl
and some tricks to sample data with unsynchronized clocks
12:33
apurvanandan[m]
Also if we send low speed clock from RFE, we will have to account for the difference in delay due to different paths, no?
12:34
Bertl
yes, but delays only result in phase difference, not in differences in frequency
12:34
Bertl
i.e. if you have two FPGA both with a 100MHz oscillator
12:35
felix_
a constant phase offset is much easiert to correct than frequency drift
12:35
Bertl
then you can assume that they do not run at 100MHz and the two clocks will never be synchronized
12:35
felix_
yep
12:35
Bertl
but if you generate a 10MHz singal from the 100MHz oscillator on one side
12:35
apurvanandan[m]
Yes ofcourse
12:36
Bertl
and transfer it to the other side, where you regenerate the 100MHz signal from a PLL
12:36
Bertl
you will get some jitter and a (unknown) phase relation, but you will have the same average frequency
12:37
Bertl
so the problem of synchronization is usually reduced to determining the right delay to correct for the phase difference
12:37
apurvanandan[m]
Yes, agreed
12:37
Bertl
okay, back to encodings then ...
12:38
Bertl
one reason to use encodings on the data is to keep a balance between '1's and '0's during any data transmission
12:38
Bertl
which is done for several (different) reasons
12:39
Bertl
for example if you want to regenerate a clock signal from the data, you would not be very successful if the data was all '0's or all '1's for a longer period of time
12:40
Bertl
in HDMI, TMDS (transition minimized differential signaling) is used, which has goal to reduce the changes between '0's and '1's
12:41
Bertl
mainly to reduce EM interference, while still keeping a balance between the two states
12:41
Bertl
what all encodings have in common is that they generate a larger code word than the original data
12:42
illwieckz_
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12:42
apurvanandan[m]
8b/10b
12:42
Bertl
and most encodings also have a number of unused or illegal states
12:42
felix_
except the line code used in sdi, but that thing's a bit uhm special... ;P
12:43
felix_
(on the larger encoded word size)
12:43
apurvanandan[m]
Oo line code :O
12:43
Bertl
sidenote here: 8b/10b encoding usually refers to the IBM encoding used in many places
12:43
apurvanandan[m]
But we won't be using that here
12:43
Bertl
while the TMDS (HDMI) encoding is also 8/10 but quite different :)
12:44
Bertl
the 8b/10b encoder and decoder is quite simple and straight forward so it might be a good option in some cases
12:45
Bertl
the TMDS encoder is a little more complicated, but we've also done implementations for HDMI so this is a good option as well
12:45
apurvanandan[m]
I find using the 8b/10b with clock recovery as most appealing option :)
12:45
Bertl
many other codes with different data and code lengths are out there and what is best suited for the projects stull needs to be decided
12:46
felix_
finds the 64b/66b line code a bit easier to implement than the 8b/10b code
12:47
Bertl
note that in all four cases, the data transfer cannot utilize hardware mechanisms to regenerate the clock from the data because the data transfer happens over 'normal' connections and not multi gigabit tranceivers featuring clock regeneration logic
12:47
Bertl
regardless of the chosen encoding, the next step is to verify the data integrity and to measure the average bit error rate (BER)
12:47
felix_
also less overhead; if you need something dc offset free, the 64b/67b code is a better fit, but i don't think that this is needed here; iirc the differential pairs are all dc coupled
12:48
Bertl
yes, in all cases there is DC coupling
12:49
Bertl
so how to test the BER of a connection?
12:49
Bertl
the simplest way is to generate (pseudo) random data on one side, send it over to the other side and compare it with the expected results
12:50
Bertl
https://en.wikipedia.org/wiki/Pseudorandom_number_generator
12:50
apurvanandan[m]
Yep
12:50
Bertl
https://en.wikipedia.org/wiki/Bit_error_rate
12:51
Bertl
there is a quite efficient implementation of linear feedback shift registers (LFSRs) we've done quite some time ago which can be used for this
12:51
Bertl
(Fibonacci as well as Galois implementation)
12:51
apurvanandan[m]
What are LFSR?
12:52
Bertl
https://en.wikipedia.org/wiki/Linear-feedback_shift_register
12:52
apurvanandan[m]
Ok
12:52
Bertl
the only thing required to use those is some kind of 'reset' synchronization
12:53
Bertl
so that both sides know when to start generating pseudo random numbers
12:53
apurvanandan[m]
Ok, got it
12:53
Bertl
then you encode those on one end, send it over, decode them on the other end and check against the known random number
12:54
Bertl
any difference needs to be further analyzed to determine the number of toggled bits
12:54
Bertl
but for a first idea just counting the errors is a good approach
12:55
felix_
xor the recieved bits with the expected ones and count the ones
12:55
Bertl
on the next layer, you want to take measures to detect (CRC) bad data and maybe even correct (ECC) small transmission erros
12:55
Bertl
again a number of options are available here ...
12:55
Bertl
https://en.wikipedia.org/wiki/Cyclic_redundancy_check
12:56
Bertl
https://en.wikipedia.org/wiki/Error_correction_code
12:56
Bertl
I don't want to go into detail here, but we will need to discuss this at a later point
12:56
Bertl
okay, you have the room now for input, discussion, questions, etc
12:57
apurvanandan[m]
Ok
12:57
apurvanandan[m]
I had planned dividing the 48 bit rgb data into 6 8-bit pieces
12:57
Nira|away
changed nick to: Nira
12:58
apurvanandan[m]
And the encode all of them into 10-bit words
12:59
apurvanandan[m]
Then serialize each of them over the 6 LVDS and use clock recovery over each LVDS separate
12:59
Y_G
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12:59
Bertl
okay, did you do a bandwidth calculation
12:59
Bertl
?
13:00
apurvanandan[m]
You said that the LVDS on Zynq can reach 1GHz
13:01
apurvanandan[m]
This means 6 Ghz of 10 bit data
13:03
Bertl
so you plan to do clock regenration on 1GHz serial data on the MachXO2?
13:04
apurvanandan[m]
No this is the max, just give me a second I am telling
13:07
Bertl
while I think this is possible (or at least you can use tricky sampling and logic to re-synchronize at this speed) it is definitely a bold endeavour
13:08
Bertl
okay, so it doesn't look like we have a lot of input at the moment, and there is still time to go into detail for the various tasks
13:08
Bertl
maybe let's figure out the next metting date and time ...
13:09
apurvanandan[m]
Firstly, In the current code we read 64 bit words at 160 MHz from RAM, I think we will have to increase that?
13:10
Bertl
the high performance readers will work up to 250MHz IIRC where 200 MHz is easier to get routed
13:11
Bertl
in any case, there are (up to) four of those which can read data at the same time
13:11
Bertl
the total achievable bandwidth is larger than the output capability of the plugin slot
13:12
apurvanandan[m]
Yeah that is what I was trying to figure out
13:12
apurvanandan[m]
Plugin slot is the constraint
13:12
Bertl
the limiting factor on the USB 3.0 plugin is probably the FTDI or the MachXO2 deserialization
13:13
Bertl
(where my bet would be the FTDI)
13:14
Bertl
so, regarding next meeting, what about Monday or Tuesday (13.05 or 14.05) again in the afternoon?
13:15
apurvanandan[m]
On Monday, Tuesday and Wednesday I am out of town
13:15
apurvanandan[m]
Have a VISA appointment
13:16
apurvanandan[m]
But will be available except that on these days
13:19
Bertl
so it would be fine for you then?
13:19
apurvanandan[m]
1Gbps * 8/10 = 0.8 Gbits per sec * 6 channel = 4.8 Gbits per sec = 0.6 GBps
13:20
apurvanandan[m]
Am I wrong here?
13:20
Bertl
not sure what you are calculating :)
13:21
apurvanandan[m]
I can't say whether I will be available at afternoon but probably will be at night ( ie around 6 pm CEST)
13:22
Bertl
_florent__, felix_: what are your preferred dates/times next week?
13:22
apurvanandan[m]
I am trying to calculate maximum output that 6 LVDS can achieve on Zynq
13:22
apurvanandan[m]
Using the technique I told
13:22
apurvanandan[m]
*8/10 isdue to encoding scheme
13:22
Bertl
well, we are sending HDMI data at 1.5GHz encoded (i.e. 1.2Gbit) per channel from the Zynq
13:23
Bertl
which is slightly out of spec for the Zynq IO Ports but seems to work reasonably fine
13:23
apurvanandan[m]
:p
13:24
Bertl
anything below 1GHz (800Mbit) per channel is in spec and should be great
13:24
_florent__
Bertl: i'm generally available during working hours, so 6pm CEST is fine
13:25
_florent__
Bertl: for theses serial link, are you going to develop everything from scratch or do you already have some code?
13:25
Bertl
6pm start of meeting or end?
13:25
_florent__
start at 6pm is fine
13:26
Bertl
great!
13:27
Bertl
well, we have bits and pieces but I guess it will end up being a development from scratch based on various example code
13:29
_florent__
Bertl: ok, i have some migen code that does a similar link for 1 lane, maybe apurvanandan[m] want's to have a look?
13:29
apurvanandan[m]
That is what I said actually, 800 Mbit on one channel that means 100MBps per channel which is again 600MByte per sec
13:30
Bertl
_florent__: yes, please share
13:30
apurvanandan[m]
That pci_screamer no?
13:30
apurvanandan[m]
on enjoy_digital
13:30
_florent__
Bertl: ok so the code here https://github.com/enjoy-digital/liteiclink/tree/master/liteiclink/serwb is doing
13:31
_florent__
a wishbone bridge over a serial link at 1.25Gbps between 7-Series FPGAs
13:31
_florent__
the lower layer are probably what you want for 1 lane
13:31
_florent__
automatic delay computation
13:32
apurvanandan[m]
Ok, thanks. Although I have trouble understanding Migen, but will try
13:32
_florent__
8b10b encoding
13:33
_florent__
apurvanandan[m]: this can be use to understand how to setup thing, but maybe Bertl wants the code in VHDL?
13:33
_florent__
the most interesting part are:
13:34
_florent__
https://github.com/enjoy-digital/liteiclink/blob/master/liteiclink/serwb/s7serdes.py
13:34
_florent__
and
13:34
_florent__
https://github.com/enjoy-digital/liteiclink/blob/master/liteiclink/serwb/phy.py
13:34
_florent__
the first one has the clocking and tx/rx datapath for 7-series
13:35
_florent__
the second one create a serial link and instanciate the 7-series serdes
13:36
Bertl
so that is based on a reference clock, i.e. 1 data lane plus a clock, yes?
13:36
_florent__
theer is also an example design
13:36
_florent__
Bertl: yes
13:37
apurvanandan[m]
Bertl , isn't the separate lane for clock the least efficient method in our case
13:37
Bertl
it really depends
13:37
apurvanandan[m]
hmm
13:37
Bertl
with 6 diff pairs, you get a 5/6 ratio if you have a separate clock
13:38
Bertl
that is 833MHz vs 1GHz on the data lanes as the same data rate
13:38
Nira
changed nick to: Nira|away
13:38
_florent__
Bertl: for now it's 1 clock lane/1 data lanes, but the code could probably be easily modified to 1 clock lane/ n data lanes
13:38
Bertl
so if you can 'only' achieve 800Mbit with clock recovery but 1GBit with a separate clock, you are better off with that extra clock
13:39
Bertl
if you manage to have an additional clock via the RFW, you are even better off
13:40
Bertl
also note that it might be a good approach to do the dynamic delay adjustments on the Zynq side if possible instead of the MachXO2 side where it seems to be more problematic
13:40
apurvanandan[m]
Ok, it will take time to decide. I got it.
13:41
Bertl
definitely needs some testing as we do not know the limits yet
13:43
Bertl
so, next serial data meeting, Tuesday, May 14th, 18:00 CEST
13:43
Bertl
which leaves Monday evening for a weekly GSoC meetup
13:43
apurvanandan[m]
Yes, so the task of this week is to go through all this reading content and report progress on Tuesday.
13:44
Bertl
yeah, get an idea what the problems are, look at potential solutions, figure out a plan how to test various things
13:44
apurvanandan[m]
What is on monday?
13:44
Bertl
find the relevant information (or the lack of it :) and be open to new ideas
13:45
felix_
next tuesday 18:00 cest works for me
13:45
Bertl
@monday nothing so far, but se6astian already suggested to make a weekly GSoC meeting
13:45
apurvanandan[m]
Some video chat or what?
13:45
Bertl
aSobhy|away: please read up and let me know if you have any questions
13:46
Bertl
apurvanandan[m]: nah, always here on IRC, way easier :)
13:46
apurvanandan[m]
But I wanted to do that :P
13:46
apurvanandan[m]
Nevermind
13:46
Bertl
feel free to video conference with the other students as much as you like :)
13:47
apurvanandan[m]
XD
13:49
Bertl
okay, then meeting concluded for today, thanks to everyone!
13:49
apurvanandan[m]
Thanks :)
13:52
Bertl
off for now ... bbl
13:52
Bertl
changed nick to: Bertl_oO
14:05
se6astian
changed nick to: se6astian|away
14:31
futarisIRCcloud
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15:16
BAndiT1983|away
changed nick to: BAndiT1983
15:18
BAndiT1983
Dev_, Y_G, usually i'm available after 5PM (german time), at the moment it's 5:18PM
15:18
BAndiT1983
or before 8AM
15:18
BAndiT1983
trello is also fine, as long as you can track all the small sub-tasks and don't lose overview
15:36
Dev__
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15:40
Dev__
Okay Bandit1983 , trello is fine for me.
15:41
Y_G
Trello works for me too
15:41
Dev__
Till now i am able to understand the codebase of OC and also the general approach for T763.
15:43
Dev__
How should i go forth from this point. Please guide
15:50
Dev__
left the channel
15:52
BAndiT1983
changed nick to: BAndiT1983|away
16:00
Y_G
From my side,I am able to understand the communication of WSServer and Daemon .
16:01
Y_G
Need to go through the part for the communication of WebRemote and the WSServer .
16:03
Y_G
Currently I'm trying to figure out how to handle multiple requests by the daemon.
16:17
BAndiT1983|away
changed nick to: BAndiT1983
16:18
BAndiT1983
Y_G why do you focus on multiple requests so much? single requests are already enough to handle at the moment, as the structure has to be adjusted so it's flexible enough but still stable
16:19
BAndiT1983
Dev_, you should tell me how you would continue the development, but to give you a starting point, check what is required for the base functionality, like static allocator and playback
16:19
Y_G
Sure ,then I'll move my focus to understanding the communication better
16:19
Y_G
and also to WebRemote and WSServer communication
16:22
BAndiT1983
there is not much to check about it, or do you have any trouble to find the endpoints?
16:23
Y_G
No,haven't went through that part of the codebase rn,Will go through today only
16:23
BAndiT1983
ok
16:23
BAndiT1983
if you need something, then just ask, will read logs later, off for walk
16:24
Y_G
" as the structure has to be adjusted so it's flexible enough but still stable " ,what structure are we talking about here?
16:24
BAndiT1983
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16:24
Y_G
Sure :)
17:00
RexOrCine|away
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17:08
Nira|away
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17:10
illwieckz_
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17:44
BAndiT1983|away
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17:45
BAndiT1983
Y_G, it's about checking if sending 2 parameters is suitable for most cases, added second one as workaround for the problem that we need to set CMV registers, so the first one would be index and second one the value or the bit map, as the registers sometimes contain multiple settings
17:46
BAndiT1983
also other things have to be checked about it, later it would also include secured connection, e.g. SSL
17:47
aombk
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19:23
illwieckz
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19:36
illwieckz
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19:49
aSobhy|away
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19:58
aSobhy
reading up ...
20:11
Kjetil
Bertl_oO: felix_ : Just a minor input that is a bit on the side of the discussion of data transfer. Is synchronization from the output module. The SDI module felix is working on has reference inputs, which should probably be used to synchronize the sensor sampling. So somekind of method to send sync data in return is probably needed. But there might be some spare lines for that?
20:42
Bertl_oO
yes, IIRC, it is planned to have a back channel anyway
20:43
Bertl_oO
so either that one is used for sending sync information or some 'low speed' GPIO can be used for that
20:49
Bertl_oO
(back as in 'return')
20:58
BAndiT1983
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20:58
Nira
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21:09
Kjetil
Let's just establish it as forward and return channels
21:11
Bertl_oO
felix_ has the details on that
21:15
aSobhy
Bertl, for my project you said 1 and 2 differential pairs, all of them are LVDS? and how they connected ?
21:22
aSobhy
also I'm free all the next week :)
21:25
Nira|away
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21:36
aSobhy
2- after calculating BER we want to read that value from a register so Is it done by JTAG ?
22:03
RexOrCine
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22:10
aSobhy
the rest of the meeting is fine to me :)
22:15
aSobhy
I have a question about the hardware I'll use
22:15
aSobhy
will you send me the required kits ?
22:23
futarisIRCcloud
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22:42
felix_
on the return channel: i think i wrote about that in the email that i linked here
22:59
Nira
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23:50
aombk
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