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does someone know how to enable the level shifter|fclk on the (linux) zynq ?

i think i've found how to manipulate register in linux (devmem)

Francky: yes, devmem is the way to go (at least for shell scripts)

bon appetit!

so i try to program and launch the zynq

i have generated the bitstream file

i've seen in the wiki that we need to launch the ps7_init script

i have put a constatn '1' to a signal routed to a pin in my vhdl code to be able to "watch" with the oscillo if the code is running or not

i.e. just cat bitfile >/dev/xdevcfg

but what is the difference with the "programmation" from vivado or xmd ?

is your linux booting as expected and do you have access e.g. via serial console?

i have a serial console acess

okay, so everything seems to be fine, except for the PL code itself :)

it should running just after the programmation ?!

the only PL related initializations are for interfacing the PS

ok but if I put a constant to a pin in the PL, no init is needed

thanks

(i.e. blink with the led :)

because in fact i don't know if the problem comes from code or hardware (i measure with the oscillo on the breakout board)

and for the second test:

what is the STARTUPE2 ?

it is the only access to the DONE output (which is the only PL controllable LED on the microzed)

i.e. : do i need to use it ?

ok, the name is misleading

so the name is correct, it is normally used to control the startup process

ok your code is working well !

because the blink_fclk code is working well without any action on the linux side

or it might just be still activated from a previous try

the registers are not set on a default state at boot ?

ok

really depends on what you have running

http://www.wiki.xilinx.com/Controlling+FCLKs+in+Linux

so it is probably not enabled in the kernel config then

for the moment

yes i start to read the zynq technical reference manual...

i've add a port on the blink_fclk entity

i had a hdc file to connect the port to a pin

where as the led is blinking (i.e = the code is working well)

most likely some kind of warning, etc was issued in this regard

[Synth 8-5397] Deprecated attribute BUFFER_TYPE found on pin Q. Please use IO_BUFFER_TYPE or CLOCK_BUFFER_TYPE. BUFFER_TYPE will not be supported in future releases.

[Power 33-198] PS7 POWER property is not specified on the PS7 instance. Power reported will not be accurate.

but the schematics is showing my added signal connecting to the right (i.e. the one i have selected in the xdc file) pin

no, but you need to power it

yes

you have three banks on the 7020 Microzed, 34, 35 and 13

aaaaaahhhhhhh so it is normal that the IO doesn't change its level :)

ok i thought that the powering could be done by the microzed itself if power was not too high

yes, you also need to configure the bank for 3.3V

you mean the property into the xdc file right ?

yep, that should do the trick

do you think i can take the 3.3V from the microzed board to power the bank ?

i make it clean at first hand

no, that bank is already powered on the microzed

ok

but when i connect the fclk to the pin, i have a ugly 50MHz signal (very ugly)

it might not be 50MHz, it might be > 600MHz and thus get strange output results

i divide the fclk0 by 8 with a bufR

it could be the configuration of the fclk in the linux side

ok in fact this is my oscillo which is bad ! :)

Hello Everybody, I should help you on the enclosure design, and will be part of the ergonomic group

it semms that i miss something to play with the emio...

I found alone ! the numbers in linux are differnts than the numbers of the emio_gpio_i signal

correct

i red this page too fast :)

goodbye

NAB flyers picked up

good night

V03 02

good night