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#apertus IRC Channel Logs

2015/04/07

Timezone: UTC


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dmjnova
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cbohnens
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03:29
Bertl
off to bed now ... have a good one everyone!
03:29
Bertl
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se6astian
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Francky
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07:54
Francky
hi all !
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se6astian|away
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08:12
se6astian
good day
08:39
Francky
does someone know how to enable the level shifter|fclk on the (linux) zynq ?
08:43
Francky
in fact the question is : how to read/write a register in linux ?
08:59
Francky
i think i've found how to manipulate register in linux (devmem)
08:59
Francky
but it seems that my PL side is not working well...
11:49
Bertl_zZ
changed nick to: Bertl
11:49
Bertl
morning folks!
11:51
Bertl
Francky: yes, devmem is the way to go (at least for shell scripts)
11:57
Francky
hey Bertl ! i go for lunch but i think i will need some help :)
11:58
Bertl
bon appetit!
12:18
Francky
i'm back
12:19
Francky
so i try to program and launch the zynq
12:19
Francky
i have the "standard" linux on the flash
12:19
Francky
i have generated the bitstream file
12:19
Francky
and programmed it by the jtag
12:20
Francky
i've seen in the wiki that we need to launch the ps7_init script
12:20
Francky
but i can't find it
12:21
Francky
i have put a constatn '1' to a signal routed to a pin in my vhdl code to be able to "watch" with the oscillo if the code is running or not
12:22
Bertl
you can upload the bitstream to the PL from linux via xdevcfg
12:23
Bertl
i.e. just cat bitfile >/dev/xdevcfg
12:23
Bertl
unless your code messes with the done pin, the blue led will light up once it is configured
12:26
Francky
but what is the difference with the "programmation" from vivado or xmd ?
12:27
Bertl
different mechanism but same result, so if your blue led is on after programming, the PL is active
12:28
Bertl
is your linux booting as expected and do you have access e.g. via serial console?
12:28
Francky
yes i can see the led going off the going on after programming
12:28
Francky
i have a serial console acess
12:28
Francky
but it is the "out of the box" linux
12:29
Bertl
okay, so everything seems to be fine, except for the PL code itself :)
12:29
Francky
ok there is no need to "init" the PL after programming ?
12:29
Francky
it should running just after the programmation ?!
12:30
Bertl
no, all "init" stuff is only for the PS side and the PS is working just fine if you are on linux
12:30
Bertl
the only PL related initializations are for interfacing the PS
12:30
Bertl
e.g. level shifters, fclks, etc
12:30
Francky
ok but if I put a constant to a pin in the PL, no init is needed
12:31
Bertl
so if you code is independant of the PS, it will work right away once it is programmed
12:31
Francky
thanks
12:31
Bertl
I can upload a "hello world" for the Microzed PL
12:31
Bertl
(i.e. blink with the led :)
12:31
Francky
it could be great
12:32
Francky
because in fact i don't know if the problem comes from code or hardware (i measure with the oscillo on the breakout board)
12:37
Bertl
http://vserver.13thfloor.at/Stuff/AXIOM/BETA/blink_done/
12:37
Bertl
and for the second test:
12:37
Bertl
http://vserver.13thfloor.at/Stuff/AXIOM/BETA/blink_fclk/
12:42
Francky
what is the STARTUPE2 ?
12:43
Bertl
a special hardened thingy like the I/OSERDES
12:43
Bertl
it is the only access to the DONE output (which is the only PL controllable LED on the microzed)
12:44
Francky
ok but it is not the thing which "start" the PL ?
12:44
Francky
i.e. : do i need to use it ?
12:46
Bertl
no, it isn't required for code not messing with the DONE pin
12:47
Francky
ok, the name is misleading
12:48
Bertl
well, the purpose of the STARTUPE2 primitive is not to blink the led per se
12:48
Bertl
so the name is correct, it is normally used to control the startup process
12:50
Francky
but you can choose to not use it, it is for that that i say it is misleading :)
12:51
Francky
ok your code is working well !
12:57
Francky
and the fclk and level shifter seems to be activated by default
12:57
Francky
because the blink_fclk code is working well without any action on the linux side
12:57
Bertl
yes, some kernels/linux systems activate them properly
12:58
Bertl
or it might just be still activated from a previous try
12:58
Bertl
i.e. unless you power down the device, most registers won't change
12:58
Francky
the registers are not set on a default state at boot ?
12:58
Francky
erf :(
12:58
Francky
ok
12:59
Bertl
sometimes the bootloader also activates some PS/PL stuff
12:59
Bertl
really depends on what you have running
13:00
Bertl
there is an fclk linux driver, which allows you to configure and read back the frequency
13:01
Bertl
http://www.wiki.xilinx.com/Controlling+FCLKs+in+Linux
13:02
Francky
i have red this wiki but i have not these files
13:03
Bertl
so it is probably not enabled in the kernel config then
13:04
Francky
it is okay because i don't need to configure them, just need to activate them
13:04
Francky
for the moment
13:04
Bertl
yup, you can also configure them via registers, but it is a little trickier
13:06
Francky
yes i start to read the zynq technical reference manual...
13:13
Francky
it seems that my code doesn't set correctly the BANK pins
13:13
Francky
i've add a port on the blink_fclk entity
13:14
Francky
and connect it to the blue_led signal
13:14
Francky
i had a hdc file to connect the port to a pin
13:14
Francky
but the level of the pin doesn't change
13:14
Francky
where as the led is blinking (i.e = the code is working well)
13:14
Bertl
double check the build log
13:15
Bertl
most likely some kind of warning, etc was issued in this regard
13:15
Bertl
also, open the GUI and let it show you the schematic
13:16
Andrej74
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13:24
Francky
the only synthetisis warning is
13:24
Francky
[Synth 8-5397] Deprecated attribute BUFFER_TYPE found on pin Q. Please use IO_BUFFER_TYPE or CLOCK_BUFFER_TYPE. BUFFER_TYPE will not be supported in future releases.
13:24
Francky
the only implementation warnings are :
13:24
Francky
[Power 33-198] PS7 POWER property is not specified on the PS7 instance. Power reported will not be accurate.
13:24
Francky
[Power 33-232] No user defined clocks were found in the design!
13:25
Francky
but the schematics is showing my added signal connecting to the right (i.e. the one i have selected in the xdc file) pin
13:26
Francky
do we need to "unlock" or "activate" the IO bank somewhere ?
13:29
Bertl
no, but you need to power it
13:29
Francky
by external power ?
13:29
Bertl
yes
13:29
Bertl
on the breakout, that's what the headers are for
13:30
Bertl
you have three banks on the 7020 Microzed, 34, 35 and 13
13:30
Bertl
and two on the 7010 Microzed (Bank 13 is missing)
13:30
Francky
aaaaaahhhhhhh so it is normal that the IO doesn't change its level :)
13:30
Bertl
yes :)
13:31
Francky
ok i thought that the powering could be done by the microzed itself if power was not too high
13:38
Francky
so if i want the io to toggle between GND and 3.3V, i need to power the bank at 3.3V ? is there another thing to take care to choose the voltage ?
13:39
Bertl
yes, you also need to configure the bank for 3.3V
13:39
Bertl
otherwise termination and voltage levels will be off
13:40
Francky
you mean the property into the xdc file right ?
13:40
Francky
set_property IOSTANDARD LVCMOS33 [get_ports {test_*}]
13:40
Bertl
yep, that should do the trick
13:41
Francky
ok i try !
13:43
Francky
do you think i can take the 3.3V from the microzed board to power the bank ?
13:46
se6astian
gotta go
13:46
se6astian
changed nick to: se6astian|away
13:46
Bertl
Francky: yes, you can, but an external regulated and power limited supply would be preferable
13:57
Francky
i make it clean at first hand
13:58
Francky
do the emio need to be powered too ?
14:05
Bertl
no, that bank is already powered on the microzed
14:05
Bertl
i.e. the peripherial outputs
14:07
Francky
ok
14:07
Francky
for information, the pin is toggling well :D
14:07
Francky
but when i connect the fclk to the pin, i have a ugly 50MHz signal (very ugly)
14:10
Bertl
try to divide it down by 10 stages (i.e. 1024)
14:11
Bertl
it might not be 50MHz, it might be > 600MHz and thus get strange output results
14:38
Francky
something is strange
14:38
Francky
i divide the fclk0 by 8 with a bufR
14:39
Francky
and i measure a period of 18Hz (yes Hz, not MHz) on the output pin
14:39
Francky
it could be the configuration of the fclk in the linux side
14:44
Francky
yep the default state of the register clk_ctrl generate a sloooow clk
14:48
Francky
ok in fact this is my oscillo which is bad ! :)
14:50
Francky
but last week end you says that the fclk should be 33MHz or something like that, so why it might be > 600MHz ?
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FrancoisGandon
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14:52
FrancoisGandon
Hello Everybody, I should help you on the enclosure design, and will be part of the ergonomic group
14:53
Francky
hi
15:04
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15:08
Francky
it semms that i miss something to play with the emio...
15:09
Francky
i try to connect the "blue_led" signal of the blink_cfg project to the emio_gpio_1 but i don't read the right value in the linux side (always 0)
15:19
Francky
I found alone ! the numbers in linux are differnts than the numbers of the emio_gpio_i signal
15:22
Francky
there are 54 (0...53) gpio reserved numbers into linux, so gpio(0) from the pl side corresponding to gpio54 on the ps side
15:34
Bertl
correct
15:35
Bertl
http://www.wiki.xilinx.com/Linux+GPIO+Driver
15:54
Francky
i red this page too fast :)
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cbohnens
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Francky
goodbye
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Francky
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se6astian
back
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se6astian
NAB flyers picked up
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francois
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se6astian
good night
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se6astian
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22:56
Francois
quick question for the inventor users
22:56
Francois
changed nick to: Guest41897
22:56
Guest41897
the model is divided in two parts right
22:57
Guest41897
V03 02
23:09
Guest41897
I found a way
23:09
Guest41897
good night
23:12
Bertl
excellent!
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