Current Server Time: 08:32 (Central Europe)

#apertus IRC Channel Logs

2019/03/07

Timezone: UTC


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RexOrCine|away
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03:15
Bertl
off to bed now ... have a good one everyone!
03:15
Bertl
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BAndiT1983|away
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07:47
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07:49
ayushi
Does submission of all tasks where only atleast one is required increase the quality of proposal?
07:49
se6astian|away
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07:50
ayushi
I mean completing more number of tasks than mentioned there?
07:51
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07:51
se6astian
hi ayushi, it doesn't - one very good task submission (with nice comments, good structure, good formating, clean solution) will be more valuable than finishing all the tasks so so
07:51
se6astian
we want to see the best of you when you create code
07:52
se6astian
not see that you can pump out lots of code
07:54
ayushi
so we can go we the easiest of all task and it won't degrade our proposal according to you?
07:58
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08:01
se6astian
each task is for a specific area of expertise matching an actual idea/project
08:01
se6astian
so choosing the one that fits best to what you want to work on later is the best choice
08:02
ayushi
ok i got it, thanks
08:03
BAndiT1983
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08:10
se6astian
if a project would fit very well with 2 coding challenge tasks and you do them both very well and the proposal is great as well then you have a high chance of being accepted
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RexOrCine
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10:21
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10:22
martin__
What are the qualification task for White Balancing Algorithms for AXIOM Beta and OpenCine project
10:49
Bertl_zZ
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10:49
Bertl
morning folks!
10:52
Bertl
martin__: this is a task proposed by one of the potential GSoC students and we still have to review and refine it
10:52
martin__
ok
10:52
Bertl
i.e. it will take a day or two till everything is ready
10:58
martin__
also all your projects allow both Verilog and VHDL, why is then all qualification tasks, mandatory to be done in VHDL ?
11:00
Bertl
because the current code is entirely written in VHDL so we require students to know VHDL in addition to any HDL they prefer
11:37
Bertl
off for now ... bbl
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Bertl
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12:19
vup2
BAndiT1983|away: ok the CLI works for me, but the webui seems broken to me, it still uses "type" instead of "command" and "get_all" instead of "get" and "available_parameters"
12:26
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12:29
vup2
looking more into it, it seems the webui has never worked with the daemon
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13:48
kr_saurabh
⢠/msg nickserv identify kr_saurabh Myi7rocksIRC!$#
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Bertl_oO
kr_saurabh: you might want to change your password for your nick
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testing
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testing
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BAndiT1983|away
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15:28
BAndiT1983
vup2, that's not completely correct, as the web UI was working, we have tested it at the hub and could switch analog and digital gain, but the part about getting parameters is true, as Francis hasn't uploaded adjusted code yet
15:39
BAndiT1983
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15:49
vup2
ok, there is also a lot more then just getting the parameters, which would as is with the control daemon
15:49
vup2
but Francis probably has adjusted that part too
15:50
vup2
what is preventing Francis from uploading the new code?
16:28
mrohit[m]
Hello! I have completed the T872, the IRC logs were helpful to clear all my doubts :)
16:28
mrohit[m]
Although I converted from 12 bits to 8 bits by directly clipping out the last 4 bits, I searched for using a non linear curve.
16:29
mrohit[m]
By googling a little bit, I found that I need to choose a curve on the basis of data I have
16:30
mrohit[m]
Using the Mean and std. deviation to choose a curve.
16:30
mrohit[m]
Is this a right direction to think upon?
16:33
se6astian
check http://files.apertus.org/AXIOM-Beta/optimal_curve.html
16:35
mrohit[m]
ok, thanks!
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se6astian
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20:35
se6astian
off for today
20:35
se6astian
good night
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se6astian
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BAndiT1983
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